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GbE line-card chip provides synchronization at the physical layer

Ottawa, Canada—Zarlink Semiconductor Inc. has beefed up its Synchronous Ethernet timing product portfolio with a single-chip Gigabit Ethernet line card synchronizer that allows service providers to deliver time-critical applications over packet-based networks in a cost-effective manner.

Priced at less than $10 each in high volumes, the ZL30107 chip provides timing and synchronization for Ethernet line cards in next-generation networking equipment supporting circuit services over IP-based architectures.

Integrating independent analog and digital PLLs, the device synchronizes with standard telecom and Ethernet clocks and generates an IEEE 802.3 jitter compliant 25 MHz Gigabit Ethernet output clock.

The ZL30107 device supports synchronous, holdover and asynchronous free-run modes of operation. In synchronous operation, the ZL30107 PLL replaces the free-running reference clock usually provided by an oscillator with a network timing reference. The device accepts three references and performs hitless reference switching.

The integrated DPLL automatically synchronizes to one of a pre-defined set of standard telecom frequencies ranging from 2 kHz to 77.76 MHz in addition to 25 MHz. The chip generates a very low jitter 25 MHz Gigabit Ethernet output clock.

When all references fail the device automatically enters holdover mode and continues to generate an output clock based on frequency data collected from past reference signals.

Zarlink and Marvell recently demonstrated synchronization over the Ethernet physical layer using their respective PLL and Ethernet PHY technologies. An application note outlining Zarlink-Marvell interoperability is available online at: assets.zarlink.com/AN/ZLAN_211_AppNote_Jan07.pdf.

Pricing: Less than $10 each in high volumes.
Availability: The ZL30107 chip is in volume production and offered in a 9 mm x 9 mm, 64-pin CABGA package.

Data Sheet: click here.

Zarlink Semiconductor, +1 (613) 592 0200, www.zarlink.com.

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