(Editor's note : the authors continue to compare these two analog/digital converter architectures. You may disagree with their (possibly biased) analysis, but it's worth seeing their perspective. And if you disagree: say so, and say swhy!)
After the seven-round fight back in April 2010 between the successive-approximation register (SAR) analog/digital converter (ADC) and the sigma-delta (S?) ADC, Figure 1 , (click here to see the full article) SAR has been quite unhappy about the judge’s decision to call it a draw.
Figure 1: S? and SAR topology
(Click on image to enlarge)
SAR is quite confident about its well-known strength in power efficiency, which was not included in the seven-rounds. SAR ADC decided to call out S? ADC for another round, focusing on power efficiency. S? ADC accepted the challenge without the least hesitation. Though S? ADC is a relative newcomer compared to SAR in the A/D conversion scene, it has been gaining significant popularity due to its high conversation accuracy, inherently monotonic, and other attributes.
Successive-approximation register (SAR)
At the start of a SAR ADC conversion cycle, the DAC is set to half-scale and a comparison is made between the voltage to be measured and the DAC's output. With each step, the DAC is updated, the next bit selected, and a comparison made. The digital representation of the input voltage is found using a binary search (“successive approximation”). The structure of the SAR decides that an n-bit SAR requires n comparison periods and will not be ready for the next conversion until the current one is complete. This means that from a power consumption perspective, power dissipation (and silicon area) scales with resolution and sampling rate.
Nowadays, almost every battery-powered device has at least one analog/digital converter (ADC) integrated into it. As low power-consumption requirements continue to become more and more aggressive, some silicon vendors have started to offer different power modes, paired up with input-bandwidth limitations, so that users have more control over the tradeoff between power and speed, resolution, and signal-to-noise ratio (SNR). For example, in the PSoC 5 Programmable System-on-chip architecture from Cypress Semiconductor, there are four power modes for the embedded SAR ADC, and the higher power settings allow higher throughput of the ADC.
Figure 2 shows the configuration of a SAR ADC and its multiple power modes: High, Medium, Low, and Minimum, respectively meaning maximum power, one-half of maximum power, one-third of maximum power, or one-quarter of maximum power. This ADC component covers any medium-speed (maximum 1-MHz sampling), medium-resolution cases (maximum 12 bits) applications.
Figure 2: SAR ADC configuration example
(Click on image to enlarge)
The different power modes have their effect on the throughput of the ADC. The lower-power modes will support lower input bandwidth and also reduce throughput for the ADC. The clock needs to be scaled down in the same proportion as the power mode, and the throughput will also be scaled by the same factors.
S? ADCs use the same integrator/comparator topology as incremental converters. Rather than integrating the comparator output in a counter, the comparator result is processed in a decimator. The decimator double integrates the input at the sample rate. The output of the double integrator is sampled at the decimation rate (typically 1/64 times the sample rate) and subtracted from the last output value, yielding a differential. (This is a sinc2 filter.)
Similar to the SAR ADC, silicon vendors are beginning to offer flexible multiple power options to meet various design requirements. Figure 3 shows an example of an S? ADC configuration.
Figure 3: S? ADC configuration example
(Click on image to enlarge)
The S? provides a low-power, low-noise front-end for precision measurement applications. It is usable in a wide range of applications depending on resolution, sample rate, and operating mode. It is compatible with 16-bit-audio, high-speed low-resolution for communications processing, and high-precision 20-bit low-speed conversions for sensors such as strain gauges, thermocouples, and other high precision sensors. In this example, power modes include: Single-Sample, Multi-Sample, Continuous, and Multi-Sample (Turbo).
In Single-Sample mode , the ADC performs one sample conversion on a trigger. Continuous-sample mode is used to take multiple successive samples of a single input signal. Multi-sample mode is similar to continuous mode, except that the ADC is reset between samples. The multi-sample (turbo) mode operates identical to the Multi-Sample mode for resolutions of 8-to-16 bits.
For resolutions of 17-to-20 bits, the performance is about four times faster than the multi-sample mode, because the ADC is only reset once at the end of conversion. When processing audio information, the S? is used in a continuous-operation mode. When used for scanning multiple sensors, the S? is used in one of the multi-sample modes. When used for single-point high-resolution measurements, the S? is used in single-sample mode.
These modes are all paired with automatic power settings to save users the hassle involved manually tuning each stage inside the ADC to achieve the optimal balance between performance and power.
Holding the sampling period, resolution, conversion rate, and clock frequency constant, power consumption is the lowest when the S? ADC is in single-sample mode. Power increases as we move from multi-sample mode, continuous mode, with the highest power consumption being multi-sample turbo mode.
The decision of the judges
Even though the SAR ADC has an advantage over S?, to some extent because of its power specifications which scale with the resolution and speed of ADC operation, the judges again call it a draw at the end. There are two reasons:
- Due to the nature of emerging system-on-chip architectures, designers must look at power from the whole system perspective instead of a single component, and the S? architecture brings more available twists and techniques to reduce on-chip power consumption.
In the example mentioned above, the other available techniques to reduce power of the S? are: a) disable the input buffer gain to reduce the overall power consumption, with a high-input-impedance front-end buffer (with programmable gain) that can be bypassed (and powered down) when not required. b) enable the internal charge pump which operates on a high frequency clock. When this option is selected, a lower-frequency clock is routed to the internal charge pump, which can reduce power by 100 to 300 µA in PSoC 5.
- The SAR ADC requires additional anti-aliasing filter for front-end processing in order to achieve the same level of accuracy of S?. The external components increase the overall power consumption in practical designs. S? converters typically require no anti-aliasing filters with steep roll-offs at the analog inputs, due to the sampling rate being much higher than the effective bandwidth.
S? converters use oversampling to spread the quantization noise across a wider frequency spectrum. This noise is shaped to move most of it outside the input signal's bandwidth. An internal low-pass filter is used to filter out the noise outside the desired input signal bandwidth. This makes S? converters good for both high-speed, medium-resolution and low-speed, high-resolution applications, without any external components required. On the other hand, the SAR ADC is usually coupled with a filter due to the lack of a front-end filter or other internal mechanisms that satisfy the Nyquist criteria.
About the authors
Andrew Siska has been a circuit designer for the past 30 years. He holds a BSEE and MBA and is currently working for Cypress Semiconductor as Senior Staff Application Engineer.
Meng He graduated from Marquette University with Master of Science degree in Electrical Engineering and has been working at Cypress Semiconductor as a product manager since 2007. You can contact Meng at email@example.com.