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Good behavioral model simulation: key to predicting first-order PLL synthesizer performance (Part 2 of 2)

(Note: you can read Part 1 of this article at www.planetanalog.com/features/showArticle.jhtml;?articleID=204800553)

Agilent ADS/RFDE capability and methodology
The Agilent RFDE and ADS tools provide today's engineer with an accurate, well-defined methodology for predicting first-order phase noise performance of the PLL in the above example. The noise-simulation capability in these tools include:

  • Linear noise analysis: s-parameter and small signal AC (noise voltage).
  • Budget noise analysis: system-level design at the block-diagram level.
  • Non-linear noise analysis: harmonic balance (HB) mixer noise figure, HB phase noise and noise voltage.
  • Transient non-linear noise analysis: noise generated by noise sources, non-linear devices and passive devices.
  • Circuit envelope noise analysis: a Monte-Carlo technique to simulate noise.

Using these tools, characterization and simulation of the PLL closed-loop phase noise was a five-step process. These steps included:

  1. Characterization of the VCO/divide-by-N chain.
  2. Modeling of the VCO/divide-by-N chain.
  3. Characterization of the charge pump (CP) and phase frequency detector (PFD).
  4. Modeling of CP and PFD.
  5. Modeling behavioral PLL functionality.

Note that behavioral modeling was accomplished using existing PLL system library models from ADS/RFDE and Verilog-A models with jitter which were obtained at www.designers-guide.org. What follows is a closer look at each of these five steps.

Steps 1 and 2 . Characterization and modeling of the VCO/divide-by-N chain
The transistor-level VCO/divide-by-N chain was simulated using the HB oscillator and noise analysis. The phase-noise modulator component from the ADS/RFDE model library was then used to “emulate” VCO/divide-by-N phase noise. Figure 3 shows the phase noise comparison between the model and HB simulation.


Figure 3: The phase noise comparison between the model (blue) and HB simulation (red).
(Click to enlarge image)

Steps 3 and 4 . Characterization and modeling of the CP and PFD
Characterization of the transistor-level CP and PFD was done using two-step simulation. First, transient analysis was performed to find PFD/CP sensitivity (e.g., CP current versus input phase difference at the PFD). The next step was transient non-linear noise analysis. Analysis was performed both with time-domain noise off and time-domain noise on.

CP noise current was calculated by taking the difference between currents with noise on and off. Jitter was calculated using the sensitivity. Jitter was then used for an I Noise source or for the PFD/CP model.

There are three methods to model PFD/CP:

  • Use the PhaseFreqDetCP component from the ADS/RFDE PLL system library and put jitter and other parameters from the above characterization simulations into the model.
  • Use the PhaseFreqDetTuned component from the ADS/RFDE PLL system library and inject noise current from jitter and sensitivity simulations using an I Noise current source in parallel to the PhaseFreqDetTuned component.
  • Use Verilog-A models with jitter coupled with characterization parameters (e.g., from www.designers-guide.org).

Step 5 . Modeling behavioral PLL functionality
Figure 4 shows the ADS schematic of the behavioral PLL.


Figure 4: The ADS schematic of the behavioral PLL.
(Click to enlarge image)

It includes behavioral blocks of the VCO/divide-by-N chain and PFD/CP, together with the circuit-level loop filter in ADS which is shown in Figure 5 .


Figure 5: The loop filter of the PLL.
(Click to enlarge image)

In this example, circuit-envelope noise analysis was used to run with the reference and oscillator frequencies. The simulation took less than 5 seconds. Post-process envelope-noise-data in data display was used for phase noise calculation from nodal noise voltage.

Results
The simulation results from the steps detailed in the previous section are shown in Figure 6 .


Figure 6: The simulated phase noise of the PLL frequency synthesizer
(Click to enlarge image)

.

Figure 7 shows the measurement of the same PLL, fabricated with the IBM CMOS7RF process, and that has every block in Figure 1 except for the LF. The difference in circuitry is that the PLL on the IC has a variable gain amplifier (VGA) following the VCO which was not included in the previous simulations.


Figure 7: The measured phase noise of the PLL frequency synthesizer.
(Click to enlarge image)

Table 1 compares the simulated and measured PLL closed-loop phase noise at certain frequencies. Taking into account the circuitry differences between the simulated and measured PLL, the simulated results can be used as a pretty good first-order prediction of the real PLL on the IC.


Table 1: Simulated/Measured PLL closed-loop phase noise at certain frequencies.
(Click to enlarge image)

Conclusion
In this article, the open-loop and close-loop phase-noise performance of a PLL has been simulated using Agilent's ADS/RFDE simulator. The transistor-level VCO/divider-by-N block was simulated using the HB oscillator and noise analysis. To complete the behavioral modeling, the simulated phase noise information was then added to the noise modulator component in the ADS/RFDE library. Next, transient non-linear noise was simulated for PFD/CP with time domain noise on and off, and jitter was calculated using PFD/CP sensitivity. Results were then added to the PFD/CP model for PLL top-level simulation.

The simulated results, based on the PLL behavior model, proved to be consistent with measured results on the IC given the circuitry differences between the simulated model and measured PLL. This work validates the idea that the real PLL performance can be predicted at first-order by using a good behavior model simulation.

Acknowledgement
The authors wish to acknowledge the assistance of Andy Howard from Agilent Technologies on RFDE/ADS simulations, as well as the support of Carlos Cardenas from M/A-COM on simulation tools.

References
1. D.B. Leeson, “A simple model of feedback oscillator noise spectrum,” Proc. IEEE , vol. 54, pp.329-330, 1966.
2. B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE J Solid-State Circuits , vol. 31, pp. 331-343, Mar. 1996.
3. A. Hajimiri and T.H.Lee, “A general theory of phase noise in electrical oscillators,” IEEE J Solid-State Circuits , vol. 33, pp. 179-194, Feb. 1998.
4. A.Demir, A. Mehtotha, and J. Roychowdhury, “Phase Noise in oscillators; a unifying theory and numerical methods for characterization,” IEEE Trans. Circuits Syst. II, vol. 46, pp. 56-62, Jan. 1999.

About the Authors
Russ Kramer is an application engineer Agilent EEsof EDA, specializing in IC business development.
Yi Fang and Wei Zhang were with M/A-COM, Tyco Electronics, Morristown, NJ.

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