Hands-on: Get started in analog IC design and fab (Part 3 of 3)

(Editor's note : This hands-on article is somewhat of a departure from our usual type of technical article, but it is not a “touchy feely” recounting of the emotional trials, tribulations, late nights, weekends, and successes of meeting and overcoming a major challenge.

Instead, it describes how an experienced engineer undertook to teach himself analog IC design, including his planning, the tools, the sequence of events, and the actual IC fabrication process. Whether you are thinking about learning analog IC design yourself, or just want to see how you can use available resources as part of self-paced continuing education regardless of your engineering career stage, you'll find it of interest and with actionable lessons and take-away information you can use.)

We are pleased to present this feature, in three parts:

  • Part 1: Goals, sources, curriculum, and “exams”, click here
  • Part 2: The thesis project and MOSIS, click here
  • Part 3: Free tools, Tanner tools, and finishing, below

Enough of the introduction, let's continue with Stephen's Lafferty's story:

Free tools for getting started
One of the things that helps make home study in microelectronics more feasible is the existence of free software tools. In his book, Baker introduces the reader to a layout program called LASI and a circuit simulator called WinSpice. Those were great for doing the assignments in my M501 course. The LASI user interface is certainly not what Windows users have come to expect but once you learn it, you can get the job done. It's just wonderful that its author makes it available without charge, so students can have something to learn with.

These days, Baker seems to have migrated to using Electric for layout and LTspice for simulation. Both of those are free and they greatly improve on the user interface. Electric is interesting and unique because it maintains the connectivity of a schematic between objects in the layout.

Instead of placing rectangles of various layers to create a MOSFET, you place an NMOS or PMOS object. The object has the essential elements of the device ready to go. You just change property values to set width and length. It's a great concept and can be very effective in layout, particularly for digital circuits.

However, I discovered by trial and error that the free tools could not get me through the actual analog chip design and layout. Unfortunately, it took months to discover the fatal flaws in some cases. During the circuit design phase, I went through using WinSpice, LTSpice and finally finished with HSpice. (SuperSpice was also considered.) With each one before HSpice, I eventually ran into a problem which I could not work around.

Convergence and noise modeling were key issues. At each change, I had to learn about the new tool and adapt the models and circuit files to the new simulator. As you can imagine, all that cost a huge amount of time, though I learned a lot. Different simulators have different MOSFET models and adapting parameters from one to another can be difficult. HSpice is the “big bucks” professional tool that the foundry's model parameters often target. Fortunately, I was able to get temporary access to it to complete the design. I would recommend that you find a way to use HSpice or an equivalent tool (see below) for simulation, perhaps through a university, chip company or some such source. The others are fine for course work, though.

One solution which I didn't try is Tanner's T Spice simulator and S-Edit schematic capture. T Spice promises HSpice compatibility and has a full suite of MOSFET models. Their premium DRC tool, HiPer Verify, can extract a hierarchical netlist from the layout and feed it to T Spice. That would have made a very nice, integrated tool set.

Tanner Tools to the rescue
The tale of software woe didn't end with the simulators. I also went through learning curves with the LASI and Electric layout editors before discovering that I could not complete the project with those. Software bugs almost trashed my layout in one case.

Another issue was that the design rule checking (DRC) reported hundreds of spurious errors. DRC is a crucial tool in chip layout. It's hard to convey how important it is that it be fast and accurate. I tried Magic but it seemed hard to use and is Linux-based.

Anyway, the layout tool odyssey also cost months of time. Eventually, I found a student version of Tanner Tools from Tanner Research, Inc. in the book “Physical Design of CMOS Integrated Circuits Using L-Edit” by Uyemura. It was a 1995 DOS version but it ran. It had a pretty user-friendly GUI, and looked like it could do the job. Clearly, it was in a different class from the free tools.

The one thing it didn't have was a technology setup file for the CMOS process I was using, though it had files for some others. The tech setup file defines the layers and their properties, the design rules and quite a few other things which are critical to supporting the process you are using. It would be very difficult to create one from scratch and chances are you would make errors. Without much hope, I contacted Tanner Tools to see if, perchance, they might still have that file available for this ancient student version.

To my surprise, Tanner did not just try to brush me off. In fact, they kindly worked with me to see if they could solve my problem. Of course, there is no way that an individual like me could afford to buy an actual Tanner license. Even though they are probably the most cost-effective commercial IC-layout software out there, there is no way that it could fit into my education budget. Turns out that they didn't have the file for the ancient student version and they no longer have a student version of the current software.

What to do? I asked if there was some way that they could make a license available long enough for me to do the layout, at a price that I could afford. To my surprise again, they didn't laugh. Instead, I was asked how long I would need the tools and what my budget was. After some discussion we were able to come to a mutually beneficial lease agreement. They gave me full tech support and had the software kit delivered overnight, Figure 6 .

Figure 6: Tanner Tools L-Edit IC layout software

(Click on image to enlarge)

I had the software installed and running in no time, and it was love at first sight. Here was a package that was totally user friendly. It's a true Windows app and does things just like a Windows user expects. It was very easy to get going. The technology file setup everything nicely for the 1.5m MOSIS process. The software is fast. Complex layouts refresh in a flash. Complete design rule checks (DRCs) execute in seconds. When you click on a DRC error, it takes you right to the problem and points-out where the violation is.

There are countless little ways in which the L-Edit layout tool helped me get the job done. For example, when I did a DRC at the top level cell and had a DRC error in a low-level cell, it didn't bug me with an error for each time the cell is used. When you click on the error, it takes you straight to the low-level cell which is the source of the problem.

You can get going quickly with the most commonly used layout features and don't have to understand all of the extra tools that are available. They don't get in the way. Gradually, I have learned more and more of the tools which are there as I needed them. I have also taken full advantage of the customization features to define shortcuts. You can see a list of the shortcuts I used here.

Tanner's tech support was excellent. They were very knowledgeable and helpful, though I didn't have to call on them much. When I got into a crunch at the end, Tanner provided the Dev-Gen layout generator and a library of pads and such at no extra charge, even though those would normally have been extra cost items.

I have to tell you: I'm a brutally honest, independent cuss and there is no way I would write a puff-piece about a tool I didn't truly like. With the Tanner software, I'm in love. This section was a piece of cake to write. By the way, I have no other connection with Tanner. They didn't even hint about what I should write. I'm just a happy user.

One more thing: The Tanner Tools have been rock-solid, stability-wise. Never experienced a bug. That's a great feeling when you have almost completed a design, everything is golden and you just don't want to mess it up. (For more details, click here.)

Finishing the chip
Getting back to the education program, layout of the chip proceeded faster than I expected. I built the large devices first and did some layout planning to optimize the effects of thermals and to minimize wiring. It's a good idea to run DRCs as you go along so that you can fix problems while changes are still easy to do.

Nevertheless, during final checking, I realized that the N+ resistors I had designed-in have a gross tendency to vary in width. At the narrowest specified width, the actual width might vary 3:1 in this process. So I had to replace those with poly resistors. Those and other such issues did cause a fair amount of rework.

Another matter which I needed to resolve was finding layouts for the bond pads. It might seem like a small thing. It's just a square of metal, right? Not really. They are quite complex. The bond pads must be integrated with protection networks and it's highly recommended that one use bond pads provided by the people handling the process.

MOSIS has bond pads available in universal GDS format but not in native form for the layout tool, so there is an import to do and issues to resolve. I needed to modify one of the pads to provide a suitable output connection without series resistance but with as much other protection as possible. Since their pads have been proven in the field, I made the fewest changes I could to preserve the assurance that they would work properly.

Working day and night, seven days per week for the last several weeks, I did finish the layout with enough time for thorough checking. I paid $200 for MOSIS to run a DRC with their big-bucks tools and was pleased that for the most part, it agreed with Tanner's basic DRC. Design rule checking software is infamous for one tool disagreeing with another and I didn't have the benefit of Tanner's high-end DRC tool. (Hey, how much could I expect for say, 10% of normal price?) However, their basic DRC is light-years ahead of what the free tools have and it's dang fast.

By the way, chances are you will not have access to a probe station. That is a combination of a microscope and some micro-manipulators with very fine needles on them, which is used to connect test equipment to nodes in your chip. If your chip has problems, you will at least want to know why. My solution is to include a second copy of the layout, with lots of internal nodes bonded-out to pins on the package. That explains why the opamp uses a 28-pin package. The test copy won't be much good AC-wise but it should help a lot in diagnosing problems with the chip, if they occur.

I did the final touchups and, lo and behold, tapeout day had arrived! The term “tapeout” comes from the old practice of recording the layout data to reels of computer tape to be transferred to the mask shop. I remember seeing the tape decks whirring in the computer room at Harris Semiconductor for a tapeout, when I did IC design early in my career. There was a special excitement in the air, as everyone knew that a new chip fabrication was being started.

These days, it is surprisingly easy to send a design to MOSIS for fabrication. With just a few clicks, L-Edit exports a standardized-format GDS file containing the layout. I used a free GDS viewer to inspect the file. Having previously established an account with MOSIS, I executed a Fabrication request form with some information about the design. Then uploaded the gds file to their FTP server. GDS files have a rather compact format and my chip only required about 500 KB. The whole tapeout process was done in minutes.

MOSIS computers perform some automated checks and send you an email confirming that the design is queued for fabrication. If you ordered a DRC in the special handling section of the Fabrication form, the results will be returned to you by email. While MOSIS only promises a one-week turnaround for DRCs, they kindly accepted my expedite requests and performed the DRC's typically within hours. I was very grateful for that as it allowed me to order another DRC for assurance, after submitting corrections to the layout. As mentioned above though, the DRCs cost money. I felt it was worth it to have a completely positive DRC before fab.

Marketing yourself
It's a great feeling to have the chip all finished and in the fabrication queue. Getting the chip made is the crowning achievement of your educational program, but you're not done yet. If you've scheduled things better than I did, you have saved coursework to come after the chip is into fab. The ten weeks or so of the fab process neatly provides a quarter for a couple more courses. Then you can evaluate the chip and write up a report on it. That becomes one more document in the portfolio which supports your training.

It won't work, though, to simply try to dump that portfolio on a prospective employer. I recommend that you create an uncluttered, one-page flyer which describes your curriculum and references a website containing the portfolio documents. An employer looks at your resume and sees the Microelectronic Training Program listed. The flyer is with the resume and serves to explain and sell the training program. You can view the flyer which I produced here.

From the impetus of the flyer, the employer can browse the documents on the website. The website need not and should not be fancy.

While they wouldn't spend lots of time reading the documents, a few spot checks hitting various parts of your work should convince them that there is real depth there. Of course, you should take any opportunity to discuss the program and be prepared to mention highlights and benefits the training provides for your work at the company.

Of course, the question remains: Will employers buy this? That remains to be seen. I have done my part to retool my career. The ball is now in their court. Stay tuned for updates!

About the author
Steve Lafferty holds an MSEE degree and has been working in electronic design for over 30-years. He was previously a principal engineer at Wegener Communications. Having just finished a two-year educational program in CMOS analog design, he is now available for employment in that or a similar field. He can be reached at, 770-664-6192.

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