Some applications require the production of multiple clocks with a synchronous, adjustable phase. Many single-chip semiconductor solutions can accomplish this for low frequency applications using the approach shown in Figure 1.
Single-chip phase-synchronization example.
In Figure 1, fOSC represents the frequency of the input clock and fOUT represents the frequency of the output clocks, assuming that all of the outputs are the same frequency but have a device-adjustable phase relationship. This approach typically results in tight skew between the outputs, so therefore the phase relationship between fOSC and fOUT is not critical.
The single-chip solution is an elegant one. Note that Figure 1 only shows two outputs, but the concepts apply to any number of outputs.
As the output frequency gets above 3 or 4GHz, these single-chip solutions start to become much less available on the market. Another challenge is that single-chip solutions do not have delay adjustments fine enough for high frequencies. For instance, a 10GHz signal has only a 100ps period, so delays would have to be a very small fraction of this period to be useful. Finally, signal-integrity issues can be a concern if one device generates all the frequencies and they need to be routed to different devices that are far apart; it may be advantageous to place each clock right next to the device it is clocking.
You can address many issues by approaching the problem with a multiple-chip solution, like the one shown in Figure 2. There are more high frequency devices to choose from if one restricts it to a low output count. It’s possible to make phase adjustments between the outputs many orders of magnitude finer, as these delay adjustments are based on the global delay through the device. Signal-integrity issues improve because you can place the clock right next to the device that needs it. However, all of these benefits do come at the cost of dealing with multiple device synchronization and variations in the delay between fOSC and fOUT between devices.
Multiple-chip clocking solution.
Synchronizing multiple devices to achieve deterministic phase
The first step to making a solution like the one shown in Figure 2 work is to achieve “deterministic phase,” which means that when you power up both devices and follow a given procedure, they will end up with the same predictable phase relationship.
Consider the example shown in Figure 3. The introduction of the divide by 2 after the 12GHz voltage-controlled oscillator (VCO) typically introduces a phase uncertainty. Every time the device powers up, there are two possible rising edges from which the divider can choose from the 12GHz signal, which leads to two different phases. For this reason, introducing a synchronization method is necessary. After the conclusion of a synchronization procedure, the phase relationship between both output clocks will be the same.
Multiple-device synchronization example.
Looking at the example in Figure 3, there are a few ways to make the phase relationship predictable. One method is to simply include the one-half output divide into the feedback loop of the phase-locked loop (PLL), which will cause the outputs to inherently be in phase and require no synchronization pulse at all. Including the output divider in the feedback path the PLL degrades PLL performance, however, especially if the output divide is large.
Another approach is to synchronize the output divides with a synchronization pulse. This pulse makes the delay from fOSC to fOUT deterministic. In the case of 6 GHz output frequency with a 100 MHz input frequency, the timing of the synchronization pulse is not critical and could likely occur during software programming of the device.
But if the output frequency is not a multiple of 100MHz – say, 6.025MHz – then it will matter which rising edge of the fOSC signal the synchronization pulse will choose. Therefore, the rising edge of the synchronization pulse needs to be timed away from the rising edge of the fOSC signal. A pin is required in such cases because the timing is critical. One approach is to use a JESD204B-compliant device that can produce a SYNC signal with an adjustable phase to the fOSC signal it produces.
Global delay of the devices
The synchronization procedure guarantees a consistent phase relationship between the outputs of both devices, but that does not mean the phase is necessarily zero. The delay through multiple devices is typically in the nanosecond range and the phase is expected to be in the picosecond range. If both devices had exactly the same global delay through the device, there would be no issue, but this global device will vary from device to device, process and configuration.
Figure 4 shows the result of two devices that are synchronized in phase but still have a 32.7ps phase error due to the differences in the delays through the devices. For a low-frequency output signal, this may not be very significant, but at higher output frequencies, the error becomes more significant and thus more of a consideration. For a 6GHz output, the phase error works out to be about 20 degrees.
6 GHz outputs from two Texas Instruments (TI) LMX2594 synchronized devices using the TI Phase Synchronization Reference Design .
The amount of tolerable global delay depends on the application. For some data-converter clocking applications, it may be possible to correct for this delay in the digital realm, so any delay is tolerable as long as it is consistent. If the application is combining two outputs for better phase noise, a 40-degree phase error may be tolerable . Other applications may require the phase error to be less than 1 degree.
For some devices, it is possible to adjust the phase after it is synchronized. For instance, the LMX2594 has an adjustable initial phase of the fractional circuitry called MASH_SEED that you can use to program precise digital delays . Figure 5 shows the results of doing so.
Adjusting digital delays with the MASH_SEED of the LMX2594.
By using these fine adjustments, you can compensate for variations between devices. For the case shown in Figure 5, the global adjustments are finer than 2fs. There is still an error of -1.6ps that you could calibrate out, but other factors will limit how close the phase can be. One consideration is that this error might be due to the measurement of the 40GSPS scope. Aside from that, the LMX2594 global delay varies on the order of 2.5ps/o C. A difference in temperature between two devices of just 1 degree would introduce about a 2.5ps of skew. So, the expectation in Figure 5 that the phase error is less than 1 degree might be wishful thinking unless you are willing to continuously calibrate the skew.
The challenge of producing clocks with an adjustable phase relationship may lead to multiple-chip solutions if the frequency is high (<4GHz). Multiple-chip solutions address some issues, but do bring challenges related to multiple device synchronization and unequal global delay. Synchronization features and adjustable global delays are among the methods that address these new challenges.