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High-performance delta-sigma ADCs ease the limitations of embedded converters

As IC technologies have progressed towards higher integration, the realization of
complete systems-on-a-chip (SoC) has replaced the discrete components that once populated boards. The benefit of such systems is reduced system cost, increased reliability, and decreased size.

IC manufacturers have integrated functions such as A/D, D/A converters,
references, op-amps, and temperature sensors with microcontrollers in order to form data-acquisition systems. While the integration of analog and digital functions has many
benefits, the use of pure analog chips for critical functions leads to increased performance.

Analog-to-digital converters (ADCs) are a crucial building block for many applications.
Their performance often defines the system performance, while innovations in ADC
technology are required for next-generation products. Precision signals from temperature
sensors, weight bridges, pressure sensors, blood glucose sensors, to name a few, all
require high-performance ADCs. Resolution, noise, offset, drift, and linearity are among the parameters defining ADC performance.

Historically, ADCs have not been available to meet the performance requirements of
many precision systems. In order to ease the requirements on the ADC, front-end
amplifiers were added to the input signal path. An external gain of x100 placed in front of
an ADC reduces the noise, offset, and drift requirements of the ADC by a factor of 100 (input-referred) but requires a precision analog-front-end design. Errors introduced by the
external amplifier sum directly with the input signal, independent of the gain used. Converters with resolution of 12 through 16-bits are readily available on complex digital chips. The resolution of these converters can be increased by one bit (factor of 2) for every doubling in external gain (Figure 1 ).



Figure 1: Increasing ADC Resolution Using External Amplifiers

One problem with adding external amplifiers is the resultant reduced input range. Signals with large offsets (such as tare voltages) may over-range the ADC input. For very high-performance systems, the amplifier design is critical. Switched-capacitor (offset and 1/f cancellation) type architectures with low-drift external resistors are required. Performance is dependent on the amplifier used and the board layout.

Alternatively, ADCs with resolutions of 20 or 24-bits can be used without the added
complexity of external amplifiers. While a 50 mV signal applied directly to a 24-bit ADC
uses only 1% of its available input range, 16 bits of precision is possible within that tiny
range.

Achieving ADC resolutions greater than 16 bits is difficult using conventional
technologies. For example, the resolution of a successive-approximation-register (SAR) ADC is dependent on the matching of an on-chip, precision DAC. Such IC technologies require on-chip trimming or calibration techniques, even to achieve 16-bits. Flash, multi-step, pipelined, and cyclic ADCs all have these limitations.

Delta-sigma ADCs enable high resolution

Delta-sigma ADCs work on the principal of oversampling, rather than component
Matching, to achieve high resolution. Multiple low-resolution conversion cycles are
combined to form one high-resolution result. As shown in Figure 2 , by combining a one-bit ADC, a one-bit DAC, an analog integrator, and a digital filter, more than 20-bits of resolution is possible.



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Figure 2: Simple Delta Sigma Analog-to-Digital Converter

At first glance, the implementation of such an architecture appears simple. The one-bit DAC is simply a switch selecting either ground or Vref , the one-bit ADC is a comparator, the digital filter is a ROM and adder, and the integrator can be implemented using switched capacitors and an op-amp.

Its apparent simplicity and tolerance to mismatch has lead to the combination of delta-sigma ADCs with CPUs and other complex digital functions on a single die. While this
Standard-cell approach enables single-chip data-acquisition systems, problems due to
digital crosstalk have led many system designers to use dedicated ADC ICs.

A critical component of the delta-sigma ADC is the integrator. The performance of this
block determines the overall noise, offset, power dissipation, and resolution. This block
combines an operational amplifier with a switched-capacitor network. It simultaneously
performs summation , D/A conversion, and integration, using an array of sampling
capacitors.

One of the most important specifications of a high-resolution ADC is noise. In order to
eliminate external amplifiers, very low noise performance is required. For example, in
order to measure 50,000 counts from a typical load cell (10mV full-scale), the ADC noise
level must be below 200nV.

Several factors contribute to the noise performance of a delta-sigma ADC. While architectural tradeoffs determine theoretical noise levels, the addition of digital crosstalk results in significant noise degradation.

Digital crosstalk degrades embedded ADC performance

Typically, an integrated circuit’s digital and analog building blocks (transistors, resistors,
and capacitors) all share a common substrate. For an N-well process, this substrate is
made from P-type material and is tied to the chip ground (the lowest on-chip voltage).
Digital circuitry injects currents into this common substrate at every switching event.

Essentially, all switching digital gates act as noise transmitters. Statically, CMOS digital
logic does not draw significant DC current, since either the N-channel or P-channel
device is off.

However, during the transition of an input/output from 0-to-1 or 1-to-0, both devices are on when the input is above Vtn (N-channel threshold voltage) and below Vdd -Vtp (P-channel threshold voltage), Figure 3 .



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Figure 3: Digital Logic Injects Switching Noise Into the Substrate

This causes a current to flow from Vcc to ground and injects a current pulse into the common substrate (Reference 1 ).

The magnitude of this pulse is dependent on the device size, process parameters (such as Vth , Cox , mobility) as well as supply voltage and temperature. The timing of this pulse is device-specific and depends on internal parasitic capacitance, temperature, logic-switching pattern, supply voltage, and bond-wire inductance.

As the digital complexity increases, the number of noise transmitters increases. Each
digital gate (inverters, NAND gates, NOR gates, complex logic, multipliers, registers, ROMs, RAMs, and so on) inject noise into the substrate. For example, a 9.4 thousand gate (kgate) digital circuit generates 2mV of substrate noise, and a 220 kgate digital circuit can generate 338 mV of peak-to-peak substrate noise (References 2 and 3 ). Moreover, complex circuits such as CPUs generate instruction-dependent noise. Different operations (multiply, memory access, load register, add) each inject different noise patterns as a function of the digital inputs/outputs (Reference 4 ).

The performance degradation due to substrate noise is difficult to control and predict (Reference 5 ). Guard rings around critical analog components can only reduce the noise by about 13dB, and for a typical, heavily doped substrate (required for latch-up immunity), the physical separation has no effect on noise coupling or its settling time (Reference 6 ). The front-end sampling capacitors and amplifier input stage used in the delta-sigma converter’s integrator act as receivers for the digitally induced substrate noise (Figure 4 ).



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Figure 4: Substrate pickup of noise by front-end analog integrator

The input capacitors are built on top of the substrate and the integrator’s switches and amplifier’s transistors are built using the substrate as their bulk connection.

Therefore, substrate noise is coupled into the integrator and summed together with the actual input signal. The parasitic capacitance between the substrate and the bottom plate of the input capacitor is approximately 10% of the total capacitance. A 100 mV substrate spike adds 10 mV of noise relative to the input signal (Vin ). If the integrator is implemented using a fully differential topology, the substrate noise is rejected by another 20 dB (Reference 7 ). This falls short of the 114 dB rejection required to reduce 100 mV of noise to below 200 nV.

As previously discussed, delta-sigma ADCs can achieve high resolution using oversampling. In order to achieve 20 to 24 bits of performance, the input is sampled 256 or more times per conversion result. Each time the input is sampled, the substrate noise is
also sampled. A typical low-noise delta-sigma ADC will sample and integrate substrate
noise over many milliseconds of total conversion time. This makes it difficult to suspend
CPU operations during the conversion cycle, or to synchronize the CPU operations with
each of the ADC's sampling periods.

Delta-sigma ADCs achieve high performance

Rather than place an external amplifier in front of the CPU/ADC chip, or shut down the
CPU during conversion operations, a high-precision external ADC can be used. In this
case, direct digitization of a low-level input signal is possible. While delta-sigma converters contain digital filters, digital I/O, and other substrate-noise-injecting circuits,
their operation is predictable and can be synchronized with the analog operations, thus
eliminating the effects of digital crosstalk.

High-performance delta-sigma ADCs do not require fine-line digital processes. Rather
than focusing on the quantity of gates and digital functionality, the focus is on
performance. Each individual circuit is handcrafted to achieve optimum precision. For
example, the LTC2442 from Linear Technology Corp.( Reference 8 ) embeds all the “hard-to-do” analog functions on one chip and leaves the digital processing for a programmer and an external CPU.

This device combines a low-noise, integrated front-end amplifier (Figure 5 ) with continuous background calibration, in order to achieve 1 part-per-million linearity (Figure 6 ) and immeasurably low drift.



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Figure 5: 24-bit, low-noise delta-sigma ADC with embedded analog circuitry



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Figure 1: One part-per-million linearity with zero drift

A factory-tuned integrated oscillator ensures line-frequency rejection without the need for external oscillators. A versatile architecture allows variable speed/resolution, with noise as low as 200 nV and speeds up to 8 ksamples/sec.

To solve digital crosstalk problems, the 50,000-gate digital filter and control was designed and laid out without the aid of automated tools. Each gate, digital signal, and
clock line was handcrafted to ensure the substrate stays quiet during the 262,000
sample periods required for each conversion result.

Conclusion

The integration of ADCs and CPUs has forced IC manufacturers to replace transistor-level design with VHDL code, synthesis, and standard-cell libraries, resulting in lower-performance analog circuitry. Manufacturers of high-performance analog components continue to handcraft each transistor to achieve optimum performance. By extending this
methodology to board-level system, designers have an advantage over those using lower-performance embedded ADCs.

References

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About the author

Michael K. Mayes is with Linear Technology Corp, Milpitas, CA, www.linear.com.

This paper was written for and presented at the Embedded Systems Conference Silicon Valley 2006. For more information, please visit www.embedded.com/esc/sv.

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