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High-Speed I/O Disintegration

Maybe this is strange for someone working at Maxim Integrated, but to me it's clear that there is an argument for not integrating everything on a single large-scale SoC (system on a chip). Sometimes, it's better to keep certain functions separate.

As an example, think of a chip where a mix of high-speed analog functions and high-density digital circuitry is required. Technology requirements are different for the two parts of this mix, with the best process for low-power, high-density digital circuits (small geometry CMOS) not necessarily suitable for high-speed analog circuits.

In the recent history of integrated circuits, the constant pressure to reduce cost and power has led to higher and higher levels of integration. Solutions that start out as multi-chip solutions inevitably end up all integrated on a single (CMOS) die. This is not just the case for multiple digital chips, but increasingly for analog-digital mixed signal solutions as well.

For the digital functions, there is a continuing drive to smaller geometry CMOS to support higher density and lower power. However, the smaller feature size of this digital process results in worse analog properties such as SNR and headroom.

Headroom tells us the amount of extra range between the actual signal voltage swing and the available range or capability. With smaller geometry devices, the operating voltage is reduced, and with it, the available signal voltage range.

With digital process nodes hitting 28nm and below, analog properties become really non-optimal. This may slow future levels of mixed signal integration, or even reverse the trend. Integrating high-performance, high-speed serial interfaces (that require analog signal processing such as equalization) with the digital circuits they support may no longer be the best solution. Instead, utilizing a high-performance, high-speed serial interface IC featuring equalization could well become the norm.

There are additional aspects of designing high levels of SoC integration that can become problematic, including power dissipation, packaging, and risk. Read “High-speed I/O: On the road to disintegration?” for a more thorough discussion of these trade-offs.

Interestingly enough, this could lead to a split where most analog functions are integrated in a single chip to match the single large digital SoC. So maybe “analog integration” is the future after all…

4 comments on “High-Speed I/O Disintegration

  1. eafpres
    March 19, 2013

    Hi Allard–a lot of people have probably seen the press over the last year or so regarding Silicon Photonics.  That integration challenge is quite huge, and the path has split into a few camps.  One camp I would call the “hybrid” camp; in those designs a sub-system is built on one substrate then bonded to the CMOS in another operation at the wafer level, and eventually a hybrid but integrated part comes out.

    Do you see this as a possible future vs. the split design for Analog/Digital integration beyond 28nm?

  2. Comfortable
    March 19, 2013

    @Allard –

    I used to think the same as you outlined, but for a while now I've come to believe otherwise.  We can all agree I'm sure that noone wants a lot of chips on a board.  Apple would like to buy 1 chip with everything on it, put it in a Jony Ive case and turn the software team loose.  So if Company A doesn't figure that out, Company B will and they will get the business.

    Take SNR, your example.  The ultrasound system engineers achieve 160dB SNR through parallel processing.  Lots of parallel paths.  It might take lots of transistors, but they are essentially free.  Going from 5V to 1V is only 14dB.  So if 100dB is achievable at 5V, and parallel processing enables 160dB, certainly there must be a way to find 14dB somewhere in the middle.  Don't you think?

     

  3. Brad Albing
    March 19, 2013

    Allard – indeed it is unusual to see someone from Maxim espousing the opinion that not everything is fair game for integration into a SoC. But of course we need to take a careful look. As engineers, we must examine the needs of a design carefully and decide on the best way to produce the design. So I hope your blog opens things up and gets a few more engineers here to argue each side of this issue. Thanks.

  4. Brad Albing
    March 27, 2013

    >I used to think the same as you outlined, but for a while now I've come to believe otherwise.  We can all agree I'm sure that no one wants a lot of chips on a board. Apple would like to buy 1 chip [snip].  So if Company A doesn't figure that out, Company B will[snip].

    Indeed, we agree that we don't want a bunch of ICs on our PC board. One chip that does what I want would be great. And one chip that does what you want would also be great. But the problem is that what I want and what you want are not the same.

    Now if I'll buy a million of the part I want and the same for you, then the IC company (or perhaps companies) will be happy o build the ICs and sell them. But if you only want 1000 pieces, then you are either stuck with continuing to have a board full of a bunch of ICs; or you can change your design and maybe come up with a design to use that same IC that I'm buying a million of.

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