# How division impacts spurs, phase noise, and phase

Editor’s note: This month’s guest author is Dean Banerjee, an applications engineer for TI’s Signal and Data Path Solutions Business Unit. He has been involved with phase-locked loop (PLL) frequency synthesizers for over 17 years. Dean has also authored two books: “PLL Performance, Simulation, and Design,” and “From Continuous to Discrete.” He holds a master’s degree in applied mathematics from the University of Illinois, and an MSEE degree from Southern Illinois University.

Introduction

It is common practice to create a desired frequency by dividing down a higher frequency. This might be done to facilitate integrating a voltage-controlled oscillator (VCO) on a single chip, create multiple frequencies from a single frequency, or create a broader frequency range. Whatever the reason, understanding the impact division has on the phase, spurs, phase noise, and jitter can be useful.

Impact of division

Phase

When a signal is divided by a value of D, it produces D possible phases. For instance, Figure 1 shows the four possible phases when a signal is divided by four.

Figure 1 Impact of division on phase

Multiple dividers of the same division value driven by the same input could still be of phase, if there is not some scheme to synchronize them. One approach is to reset the dividers, but this has to be timed away from the rising edge of the input signal. This ensures that all of the dividers start dividing on the same rising edge. Some clocking devices intended to support the JESD204B standard have a SYSREF output that could be used for this synchronization purpose.

Spurs

A spur in the frequency domain looks like a concentrated noise spike at offset frequency (fSPUR ) from the carrier. If the spur is not correlated with the carrier, then division will change the spur offset, but not always the amplitude. However, many spurs are correlated and are caused by modulation of the carrier frequency; they appear as a pair of sidebands on either side. When this type of spurs are divided by a value of D , theoretically, the spurs are the same offset with an amplitude reduced by 20 x log(D) (Figure 2 ).

Figure 2 Frequency domain with spurs impacted by division.

Although intuition might suggest that the offset to be divided by D as well, this is not the case as explained by Figure 3 .

Figure 3 Impact of division on spurs as seen in the time domain

We see that dividing the frequency reduces the frequency deviation, fDEV, by a factor of D , but the modulation frequency (fDEV) is unchanged. The spur level is given by: This formula and Figure 3 illustrates why division by two would reduce the spur by 6 dB, but leave the spur offset unchanged. Sometimes division can create spurs that are at a lower offset frequency, but these are due to other mechanisms. For instance, Figure 4 shows a situation where a spur at 100 kHz could result as the result of mixing between the 200.1 MHz output and 10 MHz input frequencies.

Figure 4 Example for 100 kHz spur

Phase noise

The impact of dividing a frequency by D signal depends on whether or not the phase noise is correlated to the carrier. Phase noise at closer offsets to the carrier tends to be correlated and is decreased by 20∙log(D). Farther out phase noise tends to be uncorrelated and is decreased by 10∙log(D). Figure 5 shows a 6 GHz signal and the result when being divided by two. At closer offsets below 1 MHz, phase noise is correlated and improved by 6 dB, but the noise floor at the farther offsets is uncorrelated and is only improved 3 dB.

Figure 5 Example of a 6 MHz signal divided by two

Division impacts Jitter

Jitter is related to phase noise per equation 2: (2)

This formula implies that if phase noise is correlated to the carrier and the divider is ideal, then jitter will be unchanged. Because the integrated noise will be 6 dB higher, this cancels with an extra factor of two in the denominator. However, if the noise is not all correlated, or the divider is not ideal, then jitter will be degraded.

Please join us next time when we will discuss phase noise cancellation in high speed data converter systems.

References

1. Banerjee, Dean. “PLL Performance, Simulation, and Design, 4th Ed” Dogear Publishing 2006.

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