I2C switches: a closer look

I2C is a two-wire communication protocol known for its simplicity. Despite this reputation, I2C does have its challenges: a limited number of bits for a unique address can create address conflicts, or multiple devices may require different input voltages. Although solving these problems may seem straightforward, there are implication challenges to consider.

The first problem I’ll tackle is the issue of limited unique addressing bits. I2C allows seven bits for addressing, but manufacturers rarely give designers the option to select all seven bits and may just arbitrarily pick an address for their device. If you choose multiple devices that all have the same address, this will cause conflicts on the I2C bus. For example, let’s say you have four light sensors that all have an I2C address of 0x75h and no enable function. If placed directly on the I2C bus, when the master transceiver sends out the device address and tries to read data from a sensor, the four devices will ACK1 and transmit data simultaneously. This could result in in the master reading the wrong bits because multiple devices are trying to transmit different bits of data at the same time.

The easiest solution is to use a four-channel I2C switch. The I2C switch will have its own unique I2C address and will require you to write to its internal register in order to set which channels will be on at a time. Placing a single light sensor on each channel enables communication with each sensor individually like in Figure 1 below.

Figure 1

Address Conflict Solution

Address Conflict Solution

In cases where multiple I2C devices require different operating voltages, you could use an I2C switch to provide the voltage-level translation necessary for multiple voltage rails (for example, if the four light sensors in the previous example also required 1.8V, 2.5V, 3V and 3.3V rails which can be seen in Figure 2 below). Let’s also say that the main I2C bus uses a 3.3V rail. I2C switches that use field-effect transistors (FETs) to connect the channels to the main bus are able to provide translation under the condition that the gate reference voltage always remains greater than the lowest pull-up voltage plus the threshold voltage. Under this condition, the FET will be in the cut-off region and its drain-to-source resistance (RDS(on)) will be large enough to keep the two voltage rails separated. If the threshold voltage for the I2C switch FET is 0.7V, then the reference voltage (Vcc for the I2C switch) will need to be at least 2.5V (1.8V + 0.7V) or less.

Figure 2

Multiple Pull-Up Voltage Example

Multiple Pull-Up Voltage Example

There is a drawback to using an I2C switch for voltage translation rather than a dedicated translator. A dedicated I2C voltage translator (pass FET) will typically have a reference voltage at exactly the lowest Vcc plus the threshold. With an I2C switch, the reference gate voltage could be lower, resulting in longer fall times and propagation delays. This happens when the transceivers on the higher voltage rails try to pull low.

The voltage on the source side of the FET needs to drop below the reference voltage minus the gate threshold voltage of the pass FET before the bus capacitance on the drain side of the FET can discharge. The higher pull-up voltage means that it takes the capacitor longer to discharge to below the reference voltage minus the threshold voltage. These delays are within the nanosecond range and should work in systems that use 100kHz and 400kHz frequencies. The delays could, however, affect buses that use faster speeds or, when used in conjunction with an I2C buffer, present issues due to the buffer’s additional delays.

An I2C switch is not the same as a multiplexer (MUX), as some device manufacturers allow multiple channels to be on at the same time. Using an I2C switch as a MUX, such as with the example of the four light sensors, should not result in any errors. For a multiple channel switch, unintended problems could occur if you don’t design the channels properly; for example, if an I2C transceiver tries to pull low while the I2C switch has multiple channels enabled at the same time with low pull-up resistors on the channels.

Figure 3 represents an eight-channel I2C switch that also translates the voltages from 1.8V to 3.3V. The RDS(on) resistance represents the impedance of the FET when operating in the saturation region. The “TransceiverPulldown” resistor is also the on-resistance of the I2C device FET, an estimated 30Ω. When multiple channels are enabled, the pull-up resistors effectively form a parallel resistor network with the other enabled channels and the main I2C bus pull-up resistor.

A problem arises when an I2C device tries to pull low to ACK; in this example, the master on the main bus sees about 600mV, which is greater than 540mV (0.3*Vcc of the master). The voltage that the I2C master must see in order to register the value as a low is typically 0.3xVcc (the voltage input low [ViL] threshold). But because the voltage is greater, it still sees the signal as a logic “1” or high. This results in the master seeing a NACK1 . To resolve this problem, simply choose larger pull-up resistors or make sure not to enable too many channels at the same time.

Figure 3

Improper Channel Design

Improper Channel Design

I2C switches can not only solve address conflict issues; they can also provide voltage translation for multiple rails, effectively replacing multiple voltage-level translators. It is important that you’re aware of some of the problems switches could bring to an I2C chain, however, so that you can resolve those issues.


1 Understanding the I2C bus by Texas Instruments. See Section 2.3 for ACK/NACK definitions.

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