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IC Performance: Challenges in Layout with CMOS Technology Nodes

Editor’s note: I am pleased to bring you an important technical blog by Fernando Lavalle, a Ph.D. student at Texas A&M University and his colleague, Suraj Prakash, who have been working and studying relevant layout dependent issues in current recent CMOS technologies. It’s great to get fresh aspects from young engineers regarding an important topic in our industry.

Besides the known benefits of advanced CMOS technology nodes, which are moving towards the ultra-small nanometer range, the layout work for mixed-signal circuits is becoming more and more challenging. Several challenges, which were quite tamed in earlier technology nodes, are coming up as a bottleneck for design performance and robustness in current nodes. For new engineers who are working with such advanced nodes, these challenges are unknown to them because most of the undergraduate and graduate level classes do not cover layout challenges. Furthermore, ignoring such effects directly leads to performance differences between expected versus observed results. Early knowledge of these layout effects is required prior to design and layout in order to lessen future unpleasant surprises. This article covers generic but important aspects of layout that are needed to be taken care for the sake of performance and design robustness. This includes process selection, layout dependent, simulation’s out-of-scope, and invisible effects.

Process Selection Effect

The foremost point for engineers is to know the type of processes. The most common processes are bulk CMOS and silicon-on-insulator (SOI); each has their own pros and cons. Bulk CMOS process can be of highly or lightly doped type depending upon designers’ needs. A highly doped substrate has low risk of latch-up compared to a lightly doped substrate. In terms of substrate noise coupling, the lightly doped substrate offers better noise isolation between circuits due to small substrate coupling1 .

The SOI process offers significant reduction in cross-talk between analog and digital circuits on the same die i.e., ease for integration2 . It provides high performance passive elements for high frequency. It also provides lower junction capacitances, which reduce overall power consumption3 . Due to aforementioned properties, it dominates the area of low power mobile applications. As SOI has no wells into the substrate; therefore, no latch-up issue occurs. Due to floating body, SOI designs exhibit threshold voltage variations, also known as history effect. It also suffers from self-heating, which can degrade analog circuit performance. Hence, knowing the process to be used is an important step for deciding which type of challenges will lie ahead during layout.

Layout Dependent Effects (LDEs)

One of the important aspects, which started to have great impact on circuit performance in newer technology nodes, are layout dependent effects (LDEs)4,5 . LDEs are among the main reasons for having performance difference between schematic and extracted level simulations. These effects include well proximity effect (WPE), length of diffusion (LOD), oxide-to-oxide spacing effect (OSE), poly spacing effect (PSE), etc. as shown in Figure 1. The WPE is due to substrate doping non-uniformity; it comes from edge effects during ion-implantation. This has a direct impact on transistor’s threshold voltage, which affects matching and performance. Another important effect is LOD, which comes from silicon stress caused by shallow trench isolation (STI). It has impact on transistor’s mobility; however, it affects NMOS and PMOS differently.

Figure 1

Layout dependent effects

A compressive stress increases (decreases) PMOS (NMOS) mobility. The impact of this effect decreases exponentially with the distance from the STI. Another effect is OSE, which reflects the amount of STI stress in transistors with different active area spacing. The PSE, which started showing significant effect in newer technology nodes, is due to the poly-to-poly distance and has an effect on transistor’s electrical parameters. Depending upon the setup of the process design kit (PDK) and circuit simulator, predicting some of these effects in schematic can be handled through simulation parameters. For circuits, usage of dummy cells and symmetricity in the design with respect to edge are some of the ways to handle such effects.

Simulation’s Out-of-Scope Effects

Among all, electrostatic discharge (ESD) and latch-up are the main out-of-scope simulation issues, which remain hidden from most schematic and extracted level simulations. ESD can be explained as a flow of electrons between two objects at different potential that come in close contact to each other6 . Device heating and dielectric breakdown are the primary failure mechanisms in ESD events. Furthermore, latch-up is a failure mechanism characterized by excessive current flow between the power supply and ground rails7 . PMOS and NMOS parasitic BJTs interact to form a positive feedback loop that creates a short between the supply and ground. Latch-up is not a destructive process as long as the device's/metal's maximum current ratings aren't exceeded. From the layout perspective, guard rings around each PMOS and NMOS structure can prevent a latch-up condition. Also increasing space between NMOS and PMOS structures decreases the BJT’s gain, hence decreasing the positive feedback loop gain. For these issues, following the PDK’s design rule check (DRC) diminishes the probability of triggering these events.

Invisible Effects

There are a few effects that cannot be identified due to limited software resources in academia. Some examples of these effects are maximum current limit and hot-spot. For high power designs, it is important to check that the maximum current limits aren’t exceeding foundry’s limit. Active and passive devices, metal layers and contacts all have specific current limits which are given by the foundry. Enforcing your layout to meet all these limits helps to decrease device, metal, or contact failures. Any of these can cause permanent damage to your circuit. An additional safety margin is recommended if the device is to be operated for long periods of time. Another effect is hot-spot, which is a die section with higher temperature than the die’s average [8]. This creates temperature gradients that can decrease circuit’s performance, matching, and mean time to failure of chips. Conventional extraction tools do not verify these invisible effects. Therefore, it is our responsibility to account for these challenges.

In conclusion, to have a working chip there is a need to take care of all the previously mentioned points during layout, some of which can be simulated in schematic and extracted level simulation or checked while running DRC. Having a basic awareness of these effects can help engineers to have a better design with no surprises during extracted simulation and/or measurements.

References

  1. D. K. Su, M. J. Loinaz, S. Masui and B. A. Wooley, “Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits,”IEEE J. Solid-State Circuits , vol. 28, no. 4, pp. 420-430, Apr 1993.
  2. J. P. Raskin, A. Viviani, D. Flandre and J. P. Colinge, “Substrate crosstalk reduction using SOI technology,”IEEE Tran. Electron Devices , vol. 44, no. 12, pp. 2252-2261, Dec 1997.
  3. B. Davari, R. H. Dennard and G. G. Shahidi, “CMOS scaling for high performance and low power-the next ten years,”Proceedings of the IEEE , vol. 83, no. 4, pp. 595-606, Apr 1995.
  4. J. V. Faricelli, “Layout-dependent proximity effects in deep nanoscale CMOS,”IEEE CICC , 2010, San Jose, CA, 2010, pp. 1-8.
  5. Tom Beckley. (2012, March). Taming the Challenges of Advanced-Node Design. Cadence, CA.
  6. S. H. Voldman, ESD: Failure Mechanisms and Models , Wiley, Aug. 2009.
  7. B. L. Gregory and B. D. Shafer, “Latch-Up in CMOS Integrated Circuits,”IEEE Trans. Nucl. Sci. , vol. 20, no. 6, pp. 293-299, Dec. 1973.
  8. M. Pedram and S. Nazarian, “Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods,”Proceedings of the IEEE , vol. 94, no. 8, pp. 1487-1501, Aug. 2006.

About the authors

Suraj Prakash received bachelor’s degree in Electrical Engineering from Indian Institute of Technology, Roorkee, India. He worked as a senior design engineer at STMicroelectronics for five years. He is current pursuing PhD at Texas A&M University since 2012. He was with Cirrus logic as an intern during May-August 2013. He is recipient of Cirrus’ Hackworth fellowship and departmental scholarships. He is holding several granted patents from USPTO. He also served as a teaching assistant during 2013 and as an editorial assistant of TCAS-II during 2014-2015.

Fernando Lavalle received his bachelor’s degree in Electrical Engineering from Merida Institute of Technology, Yucatan, Mexico. He is currently pursuing a Ph.D. in Electrical Engineering at Texas A&M University. His current research interest includes LDOs, audio amplifiers and active-RC filters.

1 comment on “IC Performance: Challenges in Layout with CMOS Technology Nodes

  1. mikeroch
    February 21, 2017

    CMOS tech nodes are very good, I loved them.

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