IMEC claims breakthrough in ADC performance

LONDON — Belgian research centre IMEC is claiming a breakthrough in SAR analog to digital converters whose performance is such that it is being targeted at software defined radio applications.

The researchers say the device is “related” to an SDR architecture and front-end IC that was devised by IMEC engineers at Louvain and first revealed at this year's ISSCC in February.

IMEC says the very low power, 0.7 mW, 50 MSamples/s successive approximation (SAR) ADC has achieved a figure of merit of 65fJ per conversion step, and adds this is 2.5 times better than the best ADC of this kind reported in research papers.

It is also said to be an order of magnitude better than the best commercially available ADC IP blocks in 90nm CMOS. The SAR ADC's power scales linearly with the clock rate over a very wide range which, the researchers suggest makes it ideal for SDR applications.

The device is implemented in pure digital CMOS technology, making it suited for scaling to the 45nm CMOS node and below. IMEC is making the deign available as “white box IP”. This suggests it will be offered with parameterized attributes that can be altered to allow scaling.

Instead of the active charge redistribution in the capacitor arrays of a conventional SAR architecture, the low-power architecture of IMEC's design uses a passive charge-sharing concept to sample the input signal and to perform the successive-approximation cycling.

In this way, the SAR operation is no longer based on voltage comparisons. It operates completely in the charge domain, which yields the much improved performance.

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