Phase noise is a critical parameter in most phase-locked loop (PLL) synthesizer applications. In radars, for example, phase noise at low-offset frequencies translates to the ability to discern between two objects that are close together. Low phase noise is also required for data-converter clocking applications in order to achieve a low signal-to-noise ratio. For receivers, phase noise helps detect weak signals. For test equipment, phase noise facilitates the measurement of lower noise signals.
Applications pushing the leading edge of performance will need better phase noise, even if it translates to more components and complexity. Some attempts to improve phase noise involve using a fixed-frequency source with a multiplier and using a narrowband voltage-controlled oscillator (VCO) at the expense of decreased frequency coverage and down-converting the VCO frequency. In this article, we will discuss the approach for down-converting the VCO frequency of a PLL and compare simulated results of this method against actual measurements.
PLL theory basics
Before explaining how to down-convert a signal, let’s review some basics of PLL theory. It is possible to use the PLL to generate a range of frequencies from a stable source. Figure 1 shows a traditional architecture for a PLL.
Figure 1 The block diagram shows a traditional PLL architecture. Source: Texas Instruments
Phase noise in the PLL can have a dramatic effect on metrics such as receiver sensitivity, bit-error rate and signal-to-noise ratios. One key parameter that affects phase noise is the feedback divider value, N, calculated by Equation 1:
The VCO frequency, fVCO, divided by the phase-detector frequency, fPD, will produce N, which multiplies the dividers and charge pump of the PLL. If you can reduce this value, you can also reduce the noise performance. In theory, it’s possible to reduce N by a factor of 2 without increasing fPD, improving the phase noise to 6 dB. If you reduced N by a factor of 2 by doubling fPD, the PLL 1/f noise does not improve, but the PLL noise improves to 3 dB. In either case, reducing N is beneficial to phase noise.
However, there are few factors that limit how low you can reduce N:
- The maximum value of fPD is limited; one thing that limits fPD is the input frequency, fOSC. In general, fPD cannot be greater than fOSC unless there is a multiplier. Many devices have an x2 multiplier that is very helpful, but dividers greater than that can often add more noise than the improvement realized by the lower N. Aside from being limited by fOSC, the maximum fPD is typically limited to a few hundred megahertz due to the architecture of the charge pump.
- The minimum value of N may be limited. For higher-frequency PLLs, N is designed to run at very high frequencies, which requires prescalers that can put limitations on the minimum N. Also, if N supports fractional values, this fractional circuitry can place additional limitations on N.
Down-converting for better phase noise
Figure 2 shows an approach that can reduce N without increasing fPD through the addition of a stable and very low noise frequency, fMIX.
Figure 2 The down-conversion architecture can help achieve better noise phase. Source: Texas Instruments
Equation 2 expresses the reduced N as:
Equation 3 shows the theoretical PLL phase-noise improvement inside the loop bandwidth for this architecture:
The loop-gain constant will affect the loop dynamics, as defined in Equation 4:
When the loop gain changes significantly, the loop bandwidth will also change, leading either to instability or a wider loop bandwidth with a high degree of peaking. Adjusting the charge-pump gain KPD will keep the loop gain relatively constant, as will a loop filter redesign.
Figure 3 shows a theoretical analysis, ignoring the noise of the mixer and local oscillator used for mixing down and any practical limitations of the PLL. The default curve in this example is for the LMX2820 wideband radio-frequency synthesizer. The device exhibits a 200-MHz fPD and a 9-GHz output frequency, and therefore an N of 45. The increased FPD curve is for theoretically increasing fPD to 9 GHz.
Figure 3 Theoretical analysis shows a PLL N reduction from 45 to 1. Source: Texas Instruments
The down-converted curve shows the theoretical phase noise when the 9-GHz output is mixed down with a noiseless 8.8-GHz output and mixer to 0.2 GHz using the architecture shown in Figure 2. For these simulations, redesigning the loop filter keeps a similar loop bandwidth.
When fPD increases by a factor of 45, the PLL noise plateau improves but the PLL 1/f noise does not. It’s still a good improvement in phase noise, but when the output is down-converted, the phase-noise performance is substantially better.
Phase-noise measurement in a default setup
Theoretical analysis of the down-converting shows promising results, but actual measurement is warranted to back this up. For this reason, results in Figure 3 were used in the test using the LMX2820-based evaluation board, with the conditions shown in Figure 4 and Table 1.
Figure 4 The design example shows a traditional PLL setup. Source: Texas Instruments
|N||Feedback divider value||45||n/a|
|VCOCAP||VCO input capacitance||70||pF|
|T3/T1||Pole R = ratio||2.77||%|
Table 1 Loop filter parameters are sown for an actual measurement. Source: Texas Instruments
We added phase noise from the 100-MHz oscillator to the simulations. Figure 5 compares the measured and simulated values. Although it seems that far-out phase noise in the simulation is a little off, the close-in phase noise shows close agreement, indicating that the PLL noise is dominating the phase noise inside the loop bandwidth even past a 1-MHz offset.
Figure 5 The graphical representation compares the measured and simulated values. Source: Texas Instruments
Because the PLL noise is dominating the close-in phase noise, there is much potential benefit to improving the PLL noise by reducing N. In this particular case, fPD has already been maximized to 200 MHz using the x2 input multiplier. Although the LMX2820 chip does have higher-input multiplier values, the use of these higher multipliers adds more noise than gained by the reduced N; so, the x2 input multiplier is the optimal choice in this case.
Phase-noise measurement by down-conversion
With fPD maximized, the next way to improve the phase noise is to reduce N by down-conversion. A clean source—typically a fixed-frequency crystal or perhaps a multiplied version of this crystal—is required for this design task. For this setup, however, we used a signal generator for convenience. Figure 6 and Table 2 show the setup conditions.
Figure 6 This is how the setup for down-converter architecture looks. Source: Texas Instruments
|N||Feedback divider value||1||n/a|
|VCOCAP||VCO input capacitance||70||pF|
Table 2 Loop filter parameters are shown for a down-converted architecture. Source: Texas Instruments
Figure 7 shows the measured result and simulation obtained from the LMX2820 chip, which has a separate input pin for the down-converted frequency. For simulation purposes, subtracting 38.9 dB from the whole noise profile scaled the phase noise of the local oscillator—or signal generator in this case—down from 8.8 GHz to 100 MHz. If the mixer had a significant noise profile, you could scale it back in the same way. In this case, a passive mixer has noise far below other noise sources in the system.
Figure 7 The measured result and simulation obtained from the wideband RF synthesizer device. Source: Texas Instruments
We made additional adjustments specific to the LMX2820 device. The use of the external mixer input pin with this device requires the use of single phase-frequency detector mode, which effectively makes the charge-pump gain half and degrades the PLL figure of merit by 3 dB. We factored this number into the simulation.
The phase-noise benefit is not the 20log(45) = 33-dB benefit, as Equation 3 predicts. The reason for not achieving the full theoretical benefit is that it’s being limited by the noise of the local oscillator to the mixer. It is possible to substantially reduce the phase noise by using a cleaner local oscillation source. Regardless, the phase-noise improvement is still substantial, as shown in Figure 8.
Figure 8 The phase-noise improvement is still substantial with down-conversion architecture. Source: Texas Instruments
The down-conversion approach and spurs
Aside from improving phase noise, down-conversion can theoretically improve spurs. Through down-conversion, engineers can improve integer boundary spurs by using the mixing frequency to shift fVCO away from near-integer multiples of fOSC. Also, by reducing N, integer PLL spurs from the charge pump will theoretically be reduced by 20log(N).
Spurs are complicated and have multiple causes, so it is hard to know the full benefits to spurs without testing. But used in the right way, the down-conversion approach could theoretically improve some spurs.
This is Signal Chain Basics blog # 164 written for Planet Analog.
- Phase noise and the Y-factor noise figure
- Impact of phase noise in signal generators
- Phase noise cancellation in high-speed data converter systems
- Perfect timing: performing clock division with jitter and phase noise measurements
- Understanding the basics of PLL frequency synthesis