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Improving Analog Design Time

Today designers are facing increasing pressure to reduce design time and time-to-market. In the digital world, automation has long been used to enable turnaround of ever larger designs in a reasonable timescale. Designers can estimate parasitics early in the design flow — at the RTL level — to see if they meet timing and power criteria. Thus design changes can be iterated relatively quickly until the design goals are met, with detailed layout following.

In the analog world, early estimation of parasitics has not been traditionally possible. Circuit simulation without parasitics extracted from real layout gets less and less useful in predicting performance as geometries have shrunk. Layout-dependent effects are difficult to estimate, and so the designer may have to wait days for the layout, and hence the parasitics, when layout is done manually. It requires an experienced analog layout engineer to take into account the matching of devices and the topologies required to give good performance, and they usually have only time to explore one layout topology. So the circuit design and layout are iterative. This is obviously not an ideal situation.

EDA companies have recently renewed efforts to bring automation to analog layout. So, for example, Helix from Ciranova (now Synopsys) and Modgens (from Cadence) are efforts to create more automation in the analog layout flow. The traditional digital philosophy of placing components, then routing them, has been found to be lacking, and existing tools are often called “analog prototyping” solutions. The problem lies in the fact that running placement without knowing the routing is difficult — the resulting placement may not be routable, or may not be dense enough.

New analog automation technology addresses this problem by considering the placement and routing as a single problem, a process known as PolyMorphic Layout. In fact, not just one solution is generated, but multiple layout topologies, each of which can be extracted and simulated to determine the optimal one to meet the required performance criteria. Pulsic’s Animate tool, for example, can generate more than 50 variants of layout for a PLL block in about a minute; the designer can then select several to extract and simulate and choose the best one to further refine:

Multiple layouts of a PLL generated automatically.

Multiple layouts of a PLL generated automatically.

The circuit designer can now very quickly try out different topologies, and experiment with different constraints in order to optimize the design. For example, the use of different guard ring structures or shielding can be tried in order to reduce unwanted noise coupling. The ability to save the constraints used to generate a particular layout means that iterations, if required, can be performed much more quickly, as can porting to new processes or PDKs.

10 comments on “Improving Analog Design Time

  1. vasanjk
    July 12, 2014

    Keith,

    It is interesting to know that ready-made variants of possible topologies for a given design block can be changed on the fly and the right one could be chosen after careful analysis. This would save quite a bit of time. Is it possible to add custom topologies and add them to the list for future use?

  2. Netcrawl
    July 13, 2014

    @Keith great post, thanks for that, there are many attempts at analog design, most have failed. analog systhesis is big disappointement, I think the problem here is that high performance physical design is inherently very demanding, it requires the designers to ddeal with multiple hierarchical symmeties- a huge daunbting task. Earlier analog technologies have not been able to manage and deal those complexities in a more effective way, they are not addressing technical issues.

    To be successful an analog physical design technologies need to work closely with experienced analog designers, they need to know what exactly the designers need. Analog designers have historically not been interested to new tools and new approaches. 

  3. samicksha
    July 15, 2014

    Blueprint or topology map is simply time saving, giving you enough time and space to analyze, even i have similar kind of questioncan we add custom design to it for personal referance and study.

  4. Keith Sabine
    July 16, 2014

    Vasanjk, good point. Adding custom topologies certainly makes sense. The implementation would be a tradeoff between complexity for the user (e.g. having to describe the topology by scripting) and flexibility. In the simplest case new topologies could be added directly to the tool. A more flexible approach might have the tool map a schematic topology to a custom pcell the user provides. Finally an API into the tool might allow a user to define a custom topology; this of course would require a good understanding of how the tool works, which would not be simple.

  5. Keith Sabine
    July 16, 2014

    Netcrawl, agreed than analog designers are generally happy to use tried and trusted methods in the main. Automation will never be a panacea for everyone, but as geometries go down the manual layout method is becoming increasingly time consuming due to rule complexity. It is here where automation can play a part in the overall design methodology.

  6. vasanjk
    July 16, 2014

    Keith

    As the goal of every software automation is to provide a high degree of abstraction hiding the intricate details of the application, it makes sense to have templates which could be customized to a level while maintaining the simplicity.

     

    Over time, one can master the art and create and share several custom made templates and share them across.

  7. Netcrawl
    July 17, 2014

    @Vasanjk, until now the design of analog has scarcely been automated at all, but as the cost of ASICs and SoCs grows, momentum is growing to bring analog into a new height- some sort of system-level interplay, which is now taking place betwwen software  development and hardware design tools.

  8. vasanjk
    July 18, 2014

    “System Level Interplay”

    Netcrawl

     

    That's precisely my worry. Such high level integration takes the fun out of hands-on design. For a budding engineer, there is no necessity to understand how a simple quad op amp can be wired as an instrumentation amp. This kind of abstraction could kill the fun factor and,most importantly, could restrict fundamental understanding of the underlying principles.

  9. Vishal Prajapati
    July 22, 2014

    I don't have experience with IC physical layout design but I do have extensive experience with PCB design.

     

    As far as my experience goes, I have seen the open source as well as most expensive software have in built auto routing capabilities. But none of them have given aesthetically good design. The autorouted design is no where good enough compared to manually routed designs.

     

    I think this analogy will work in case of IC also. Auto routed layout will not be comparable to experienced manual layout. No matter how much rules we define for layout.

  10. vasanjk
    July 23, 2014

    Well said. Automation in design can get us to a certain level in the process in a shorter period of time, but, from then on, manual intervention and power of ingenuity is necessary to get the output.

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