Locating the source of low phase margin
Even the simple circuit of Figure 1 seems to be suffering from a low phase margin condition as described in Reference 1 with a sharp resonance at 165MHz. It is important, even in lower speed signal path applications, to check higher frequencies for trouble.
Wideband small signal simulation using the 150Mhz THS4551 FDA.
The poor phase margin here is a combination of factors. The inductive open loop output impedance at higher frequencies (Figure 68, Reference 2) reacts with the feedback capacitive load to create significant phase shift right at the output pin voltages. The feedback capacitor also shapes the noise gain back to the differential inputs down to 1V/V at high frequencies extending the Loop Gain (LG) =0dB crossover out high enough in frequency to find a 185o phase shift around the loop at crossover. Simply removing those feedback capacitors shows a stable result in Figure 2. This signal gain of 3V/V is a noise gain of 4V/V showing a bit of bandwidth extension to 45.5MHz over a simple 135MHz Gain Bandwidth Product (GBP) divided by 4 expectation of 33.7MHz. There is also no hint of stability problems at higher frequencies as there is no sharp peaking in the response.
Simple gain of 3 circuit with no feedback capacitors.
Going back to a feedback pole at 800kHz, whether this causes a problem or not also depends on the load. Changing to a more typical Successive Approximation Register (SAR) driver RC load (Reference 3, driving an 18bit, 2MSPS SAR) shows a lower resonant peaking at a much lower frequency – but probably not oscillating. The much heavier load at lower frequency has interacted with the open loop output impedance to attenuate the available feedback voltage at a much lower frequency than the 500Ω load. This has the effect of pulling back the LG=0dB crossover frequency to where the higher order poles of the THS4551 open loop gain (Figure 66, Reference 2) have not added as much to the loop phase shift. Another way of saying this is the loaded Open Loop Gain (Aol) response for the THS4551 shows a much lower frequency LG=0dB crossover. Note the measurement point here is still across the FDA outputs – not the final 1nF load. The instability potential is in the FDA and looking at the filtered response to the load often masks problems – both in simulation and on the bench.
Bandlimited gain of 3 circuit with heavy RC load.
Setting up this circuit in the LG simulation of Reference 1, show a LG=0dB phase margin at 49MHz of 15o . So, while this is not oscillating, some work to improve the phase margin would be warranted. The approaches shown will apply to any external combination of loads and feedback networks (including Rauch or Multiple FeedBack [MFB] active filters) that might be putting the device into a low phase margin condition. We will continue with the RC loaded example of Figure 4 as a more real example in a data acquisition application.
LG=0dB phase margin extraction for the circuit of Figure 3 showing 15<><> phase margin.
Circuit options to improve phase margin while retaining the desired amplifier operation
Since we know the reactive open loop output impedance is part of the problem, simply adding inside the loop output resistance can often improve the phase margin quickly. This has the effect of reducing the phase shift in the output voltage before it gets fed back to the inputs through the feedback network. Simply trying 10Ω inside the loop gives the 34o phase margin of Figure 5. These resistors have proven to be more effective if the feedback capacitor is connected on the output side of them.
Improved phase margin solution using inside the loop output resistors.
Adding these resistors inside the loop should be done with some caution as they will reduce the available output voltage swing in some cases. Keeping these relatively low (< 20Ω) will limit that degradation. While this may be enough in this case, there are other application circuits that need more phase margin improvement.
The other issue reducing phase margin in this circuit is that the feedback capacitor is shaping the noise gain over frequency to 1V/V. Most FDAs are nominally designed with equal gain and feedback resistors to give a signal gain of 1 and a noise gain of 2V/V when no feedback capacitor is in place. That nominal resistive loaded design point usually targets a phase margin between 40o and 60o . A LG simulation using all 1kΩ resistors shows a 47o nominal phase margin design for the specification set point used in the THS4551 datasheet (Reference 2).
Nominal phase margin simulation for the datasheet specified gain of 1 with all 1kΩ resistors
A lower noise gain condition, without introducing the added phase shift of a feedback capacitor, can be emulated by increasing the input resistors as shown in Figure 7. Here, those 10kΩ input resistors reduce the noise gain to 1.1V/V showing a very low 13o phase margin. This low phase margin at the 90MHz crossover agrees with the measured peaking at 90MHz for a gain of 0.1V/V in Figure 1 Reference 2. This also illustrates the risk of lower noise gain phase margin designs inherent in simply adding feedback capacitors for signal path band limiting.
Lower noise gain loop gain simulation.
Going back to the partially improved phase margin application circuit of Figure 5, one common way to shape the noise gain up with frequency is to add differential input capacitance across the FDA inputs. At higher frequencies, this capacitor (Ct ) acts with the feedback capacitors (Cf ) to shape the noise gain up to 1+2 Ct /Cf dropping the LG=0dB crossover frequency lower to a higher phase margin condition. Figure 8 shows a 500pF differential Ct across the inputs giving a higher frequency noise gain of 5V/V and improving the phase margin to 48o by pulling the LG=0dB frequency back to 12.9MHz.
Improved phase margin using a differential input Ct to shape to higher noise gain.
For highly reactive output impedance devices, adding differential input C seems to work best along with the inside the loop output resistors. Less reactive open loop output impedance devices can often get very good results with just the input Ct added. Recall, this only works in the context of a feedback capacitor in place as well. That could be the simple filter pole in the signal path being shown here, the feedback capacitor of an MFB active filter design (Reference 4), or intentionally added to allow this noise gain shaping at higher frequencies to improve phase margin (Designing Attenuators, section 9.1.6, Reference 2). Going back to a closed loop simulation, with these two-phase margin improvements in place, gives the stable wideband response of Figure 9. Here, the F-3dB is 864kHz where the slightly higher curve removed the differential input Ct capacitor. In this case, just using the two 10Ω resistors inside the loop was adequate and the differential input Ct is optional. Putting a place in the layout for that capacitor is a free way to future proof your design for phase margin problems arising later in changing FDAs, loads, or RC feedback networks.
Closed loop response with phase margin improvements
Simple and common FDA (or op amp) application circuits can be operating with lower phase margin than sometimes intended. This is becoming more likely as RR output devices come with highly reactive open loop output impedances (Reference 5). One step to isolate that from a reactive load is to add a low value, inside the loop, output resistor(s). Continued IC development in this area might well consider adding those resistors on chip to improve the phase margin in common application circuits. Often, those resistors might be enough but adding a place for a differential input capacitor always leaves the option to shape up the noise gain at higher frequencies if there is already a feedback capacitor in the intended application circuit. Using that differential input capacitor will incrementally degrade the Signal to Noise Ratio (SNR). Use as low a value (or none) as possible to achieve the target phase margin.
These issues are only becoming apparent as the vendor models have improved to include a multipole open loop gain and more accurate open loop output impedance models. It is not always the case the necessary level of detail is included in the model – especially for older devices. Testing those models for their necessary small signal response elements might be prudent. Alternate devices that might have similar phase margin hazards, and fixes, are listed in Table 1. Testing the THS4561 online model shows it to have a similar reactive open loop output impedance shape as the THS4551. It is unclear if the other two FDAs shown would require any phase margin improvements as their data sheets only show closed loop output impedance plots.
Similar negative rail in (NRI), rail to rail out (RRO) FDAs for precision ADC driving.
References for fixes to low phase margin article:
- Planet Analog, Aug. 2018, Michael Steffes, Extracting Loop Gain and Phase Information from Simulation
- TI, THS4551, Low Noise, Precision, 150-MHz, Fully Differential Amplifier
- TI Designs, Jan. 2018, Taras Dudar, Dylan Hubbard, ADC voltage reference buffer optimization reference design for high performance DAQ systems
- Planet Analog, April 2018, Michael Steffes, Designing higher frequency active filters to drive differential input high speed ADCs
- TI Analog Applications Journal, 3Q2016, Collin Wells, Miro Oljaca Modeling the output impedance of an op amp for stability analysis