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IMS2016: Preview and Preparation

It is that time of year again with IMS2016 on the horizon this week in San Francisco. It is something I look forward to each year with much anticipation. This year is a bit bittersweet for me as this could possibly be the last time I attend the show for a while. After the show is over and we move into June I’ll be transitioning product groups at Analog Devices and will begin supporting our space products in the same type of role I am in currently as an applications engineer. I’ll still be blogging here about high speed ADCs for several months as I work through my queue of blog topic commitments (which will also give me some time to get my feet a little wet with space products). I thoroughly enjoy participating in the IMS show each year and hope that I can work this into my new role, but it is uncertain at this time for me how that may occur. However, as you’ve probably hear many times the common saying is “Where there is a will, there is a way.” and there is certainly will present! But I digress; let’s discuss the preparation for IMS2016 and preview the show a bit.

As you know from my past blogs on the IMS show there is a significant amount of effort in preparing for such an event and this year for me was even a bit more effort for me in particular. There is a push from customers and the industry to show systems level solutions so I was a bit more ambitious with demo plans this year with the help of several of my colleagues at Analog Devices. A very special thanks to these guys; you know who you are! As we began our preparation meetings several months ago I worked to collaborate with colleagues within our different product groups that produce high speed amplifiers, high speed clocking devices, and RF/µW products. The result is the demonstration circuit with the block diagram that is shown in the figure below.

Block Diagram Showing the Demonstration Signal Chain

<>Block Diagram Showing the Demonstration Signal Chain

The demonstration incorporates many cutting edge products from Analog Devices. Of course, to me as the ADC applications engineer, the centerpiece is the 14-bit quad channel 500 MSPS ADC. The ADC can be configured to support one JESD204B link or can be configured to support two JESD204B links. In a system where two channels are used for main receive and two channels are used for DPD (digital predistortion) the user can take advantage of the two link operation. This allows the JESD204B link supporting the main receive function to be unperturbed while any necessary adjustments or reconfiguration can be supported in the JESD204B links supporting DPD. This is the idea behind how the demonstration is configured. Two channels of the quad ADC are configured to emulate a main receive application while the other two channels are configured to emulate a DPD application.

First let’s start with looking at the clocking network for the demonstration. The HMC7044/HMD7043 phase synchronization board is used to provide the 122.88 MHz reference to the ADF5355 which in turn generates both the ADC clock input at 1966.08 MHz and the LO input (filtered by a band pass filter from TTE) of 7864.32 MHz to the ADRF6880 microwave demodulator. The ADF5355 has an on chip doubler and divider which allows the main VCO to run at 3932.16 MHz to be able to generate the 7864.32 MHz and 1966.08 MHz output frequencies. The 1966.08 MHz input is then further divided by the clock divider within the quad ADC to 491.52 MHz. The beauty of this clocking configuration is that it can allow up to 2041 clock signals for applications that incorporate massive MIMO (multiple input multiple output) or phased antenna arrays. The Keysight DSA series oscilloscope is utilized to show the phase synchronization from the multiple outputs of the HMC7044/HMC7043 phase synchronization board. Now that we have an idea of the clocking structure let’s look at the analog inputs to the ADC.

On the main receive side a Keysight MXG series signal generator provides an LTE modulated IF (intermediate frequency) input of 115.1 MHz. In an interesting use of a 90o hybrid splitter, a signal emulating a quadrature input signal is produced. This is input to the ADL5567 which provides gain for the signals and then the two signals are input into channels C and D of the quad ADC. In order to reduce harmonics and prevent unwanted frequency aliasing a band pass filter from TTE prior to the hybrid splitter. A second MXG series signal generator could have been used, but one needs to be mindful of space in a demo booth and, of course, logistics in arranging several pieces of equipment!

On the DPD side the input to channels A and B of the quad ADC are where things get interesting. Recall that we have the ADRF6880 which receives it’s LO input of 7864.32 MHz from the ADF5355. The microwave frequency input to the ADRF6880 is provided from a PSG series signal generator which provides an LTE modulated microwave frequency input of 7.942 GHz. It is gained up via a low noise amplifier, the ADL5721. This results in a quadrature IF frequency output from the ADRF6880 of 77.828 MHz that is input to channels A and B of the quad ADC. Last, but certainly not least, I should make sure to mention the data capture board for the ADC which is the ADS7-V2 show in the figure. This board establishes the JESD204B link with the quad ADC and passes the data over to a desktop or laptop computer to display the FFT in VisualAnalog. This also allows for control interfacing of the quad ADC from the computer via ACE software. Both VisualAnalog and ACE are software developed by Analog Devices to control and evaluate products.

Now the next question you may be asking is how in the world all this will fit onto a demonstration booth where generally limited space is available. After all we do not have the space of an entire lab at our disposal nor do we have all the equipment readily on hand. Well, let’s look at how this worked out. I had two Plexiglas panels fabricated to accommodate the various evaluation boards necessary to build up the demonstration. Two panels were used in order to floor plan the booth to accommodate the evaluation boards as well as the Keysight DSA series oscilloscope, Keysight MXG series signal generator, and Keysight PSG series signal generator. This can be seen in the floor plan figure below.

Demonstration Booth Block Diagram Layout

Demonstration Booth Block Diagram Layout

The dimensions are not shown but the grey outline in the background is the demonstration booth platform area which his approximately 27.5” wide and 37.5” deep. This yields just enough room to have the MXG series signal generator stacked on top of the PSG series signal generator sitting beside the DSA series oscilloscope. The rectangular Plexiglas display containing the HMC7044/HMC7043 phase synchronization board, ADF5355, ADRF6880, and ADL5721 sits just in front of the test equipment at the front of the demonstration booth platform. The more square Plexiglas display containing the ADL5567, ADS7-V2, and the quad ADC sits on top of the two stacked Keysight signal generators. Quite an impressive display of products in a signal chain with a large amount of capability on such a small demonstration booth platform area!

I encourage you to drop by the Analog Devices booth at IMS2016 this year in San Francisco and take a look at this intriguing demonstration that utilizes many different products to showcase the capability that Analog Devices brings to the table to help our customer meet challenging system designs requiring high performance and low power components. I'd like to offer a special thanks to my many colleagues at Analog Devices for helping bring all these components together for this demonstration. I’d also like to offer my sincere gratitude to Keysight for the use of their equipment. We have many more interesting demonstrations like this. Please come by and check them out at the Analog Devices booth. Thanks for reading and I hope to see you at the show!

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