In my previous blog, Which Is Better: SAR or Delta-Sigma ADCs?, I gave an overview of the delta-sigma and SAR (successive approximation register) ADCs. I discussed the technique of oversampling as it relates to signal-to-noise ratio (SNR) and effective number of bits (ENOB). The oversampling technique is most often used with the delta-sigma ADC; but it's also useful with the SAR ADC. We will dive in a bit deeper to see how this works. First, a quick summary of the previous blog's important points.
High-performance data acquisition signal chains used for spectroscopy, magnetic resonance imaging (MRI), gas chromatography, vibration, oil/gas exploration, and seismic instruments demand a high dynamic range (DR) in addition to reduced power, area and cost. One of the ways to achieve a higher dynamic range is to oversample the converter to accurately monitor and measure both small and large input signals from the sensors.
There are a number of other ways to increase the dynamic range of an ADC such as operating multiple ADCs in parallel and digital post processing the output to get the averaged result or using programmable gain amplifiers. However, some designers may find these methods to be cumbersome or impractical to implement for their system mainly due to the power, space, and cost reasons. This technical blog focuses on the oversampling of high throughput 5MSPS, 18/16-bit precision SAR converters by implementing a straightforward averaging of ADC samples to achieve the increased the dynamic range performance.
Oversampling is a cost-effective process of sampling the input signal at a much higher rate than the Nyquist frequency to increase the signal-to-noise ratio (SNR) and resolution (ENOB) that also relaxes the requirements on the anti-aliasing filter. As a general guideline, oversampling the ADC by a factor of four provides one additional bit of resolution, or a 6dB increase in dynamic range (DR). Increasing the oversampling ratio (OSR) results in overall reduced noise and the DR improvement due to oversampling is ΔDR = 10•log10 (OSR) in dB.
Besides oversampling with a delta-sigma ADC, oversampling a high throughput SAR ADC can improve anti-aliasing and reduce overall noise. In many cases, oversampling is inherently used and implemented well in delta-sigma ADCs with an integrated digital filter and decimation functionality. However, the delta-sigma ADCs are generally not suited for fast switching (multiplexing) between input channels. As shown in Figure 1, the basic oversampling modulator in delta-sigma ADC shapes the quantization noise such that most of it occurs outside the bandwidth of interest, resulting in increased overall dynamic range at low frequencies. The digital low pass filter (LPF) then removes the noise outside the bandwidth of interest, and the decimator reduces the output data rate back to the Nyquist rate.
5MSPS, 18/16-bit precision converters
As an example of how this can work in practice, let's look at the AD7960 and AD7961 devices. These are 18/16-bit ADCs (respectively) that can convert at up to 5MSPS. They use a proprietary capacitive digital-to-analog technology to reduce noise and improve linearity without latency or pipeline delay. The low noise floor is achieved due to a combination of low RMS noise and high throughput. That makes these ADCs suitable for oversampling applications.
The AD7960/61 series operates from 1.8V and 5V supplies and dissipate only 39mW at 5MSPS when converting in self-clocked mode and 46.5mW at 5MSPS when converting in echoed-clock mode. The power dissipation scales linearly with sample rate, as shown in Figure 2, making it suitable for low-power portable applications.
AD7960/61 evaluation setup
The AD7960/61 series converts the differential voltage of the antiphase analog inputs (IN+ and IN−) into a digital output. The analog inputs, IN+ and IN−, require a common-mode voltage equal to one-half the reference voltage. The low noise and low power AD8031 amplifier buffers the +5V reference voltage from the low noise and low drift ADR4550 and it also buffers the common-mode output voltage (VCM) of the AD7960/61.
The low noise and ultra-low distortion ADA4899-1 is configured as a unity gain buffer and drives the inputs of the AD7960/61 with a 0V to 5V differential anti-phase (180° out of phase with each other). The circuit uses supplies of +7V and −2.5V for the input ADA4899-1 drivers to minimize power dissipation and to achieve the optimum system distortion performance. The simplified schematic of evaluation set up using the EVAL-AD7960FMCZ daughter board and EVAL-SDP-H1 controller board is shown in Figure 3.
For a larger image, click here.
In part 2, we will continue our look at the AD7960/61. We will also look at the available Eval board and software that can provide analysis. We'll see how well these ADCs do or don't perform. The Eval board makes it easy to see performance by looking at the FFT output from the ADCs.
- Which Is Better: SAR or Delta-Sigma ADCs?
- ADC Noise: Where Does It Come From?
- Interleaving Spurs: The Mathmatics of Timing Mismatch
- ADC Basics, Part 9: PGA Embedded in an 8-Channel, 12-Bit SAR
- Signal Chain Basics #80: Optimizing Power vs. Performance for a SAR-ADC Drive Amplifier
- ADC Guide, Part 13: Input Impedance
- Data Converters in Massively Parallel Analog Systems
- ADC Basics, Part 4: Using Delta-Sigma ADCs in Your Design
- ADC Basics, Part 3: Using Successive-Approximation Register ADC in Designs
- ADC Basics, Part 2: SAR & Delta-Sigma ADC Signal Path