In addition to the “hidden analog” at the 2014 International Solid State Circuits Conference, which kicks off Sunday, February 9, there'll be a lot of “out in the open” analog. Some of it will be very impressive. Some good places to look are always the communications sessions.
You can start on Monday with Session 2, “Ultra High-Speed Wireline Transceiver & Techniques.” At Gbit/s rates, digital signals look more analog than digital. Regardless of the coding scheme used, they need to be cleaned up before the data can be extracted, so high-speed equalizers are needed. And somewhere there is a PLL that needs to exhibit sufficiently low phase noise and jitter to generate or regenerate the digital bits. This session will cover all of these… up to a transmitter for 400GbE.
If Real RF is your thing, head down the hall to Session 3, “RF Techniques.”
The first half of the session is devoted to various ways to make more effective transmitters and power amplifiers for portable applications. One paper describes an antenna impedance and tuning chip for 3G and 4G PAs. One of the problems that handset PA guys wrestle with is the variability in the antenna impedance when the handset moves near things like a human head.
Other papers tackle power amplifier topologies such as EER (Envelope Elimination and Restoration) and the Doherty amplifier, where high-efficiency, non-linear amplifiers are made to look linear — this is critical with the complex waveforms of modern cellular systems, where linear amplification is needed but linear amplifiers are notoriously inefficient. The second half of the session deals with receiver techniques.
If you are a “power guy,” Session 4 is all about DC-DC converters. They come in two flavors: Either multi-watt-output designs trying to reach high efficiency, or lower-power switched-capacitor circuits with limited power output but decent efficiency and small chip area.
If you don’t get enough high-speed datacom in Session 2 on Monday, then Tuesday offers some more in Session 8, “Optical Links and Copper PHYs.”
You can tell there’s analog content when one of the papers refers to the “rail-to-rail Class AB output stage in 28nm CMOS.” Session 9 is another RF session, but focusing on low-power wireless systems.
However, don’t be fooled. You may think that these would be low-data-rate chips, but one paper describes a 500 Mbit/s IR UWB transceiver that consumes just 13.3 mW. And if you feel the need for speed, Session 14, “Millimeter-Wave/TeraHertz Techniques,” is a collection of university papers dealing with the problems associated with those speeds, such as VCOs and synthesizers running at 250 to 300 GHz in CMOS.
Yes, that’s 300 GHz.
What sessions at ISSCC are you planning to attend this year? Does this year’s conference cover what you are looking for? Let us know in the comments section right here.