Integrated Capacitive PGAs in ADCs, Part 1: Redefining Performance

Editor’s note: I am delighted to bring you a two-part tutorial on Integrated Capacitive PGAs in ADCs by our two guest bloggers Miguel Usach and Gerard Mora-Puchalt, from Analog Devices, Inc.

<>Capacitive PGA Circuit Description and Functionality

Sigma-delta analog to digital converters (SD ADCs) are widely used in applications using sensors with small responsivity and reduced bandwidth, due to the high dynamic range offered by this architecture.

The SD converters base their operation on two principles: over-sampling and noise shaping. In general and for a given band of interest, the dynamic range improves by 3 dB every oversampling factor of 2 (assuming white noise spectrum).

The second benefit in a SD converter is the noise transfer function. It shapes the noise to higher frequencies, which reduces even more the quantization noise at the band of interest.

Input Buffer

One of the disadvantages of oversampling architectures is that the requirements for an input buffer to drive the SD modulator may become more stringent as compared with other architectures that operate at lower sampling frequencies. Moreover, in sensing systems, presenting a very high input impedance with high precision to the sensing element is critical for the accuracy of the measurement. This makes the requirement for input buffers even more critical.

Integrating an input buffer generates other challenges. The SD modulator offers very low noise at low frequencies but any additional component like the input buffer will add thermal noise and, more importantly, flicker noise at low frequencies.

In addition, the offset of the buffer may contribute to the overall system error. The offset can be compensated by a system calibration but if the offset drift is relatively high, this approach may become impractical.

The typical way to solve these two problems is by chopping the inputs and outputs of the buffer. By chopping the inputs, the input frequency is modulated to higher frequencies. The buffer offset and flicker noise remain at their original low frequencies as they are not affected by the input chopping, as shown in Figure 1a.

The output de-chopper mechanism demodulates the input frequency back to base band, while modulates the offset and flicker noise added by the buffer up to higher frequencies that will be removed by the ADC low pass filter.

In some cases, the input buffers are replaced by a resistor-based instrumentation amplifier (resistive PGA) to accommodate a small sensor signal to the full modulator input range, maximizing the dynamic range. Just note that a resistor-based instrumentation amplifier is preferred over a differential resistive amplifier due to the higher input impedance required in discrete sensors, as shown in Figure 1b.

Figure 1

The main restriction in using this amplifier topology is the limitation on the common mode voltage, especially with gains other than one, as the resistive PGA has a floating common mode that depends on the input signal.

Additionally, the resistive network mismatch and its drift is also a concern in the overall error budget as it may have an impact on most of the precision specifications.

To avoid these limitations, recent ADI sigma delta converters have employed a capacitive PGA where the gain depends on the capacitor ratios, as shown in Figure 2.

In order to amplify DC signals, the capacitive PGA introduces a chopping mechanism at the PGA inputs, the DC input signal is modulated to the chop frequency, and then it is amplified by the capacitive amplifier. Finally, the signal is demodulated back to DC by the output de-chopper. Additionally, the amplifier offset and flicker noise is modulated to the chop frequency and low pass filtered at a later stage.

Figure 2

Capacitive PGA. (Some blocks have been removed for clarity)

Capacitive PGA. (Some blocks have been removed for clarity)

There are some benefits associated with this capacitive architecture as compared with the resistive one:

  1. Better noise versus power trade-off as it contains less noise sources.
  2. Capacitors offer a wide range of advantages over resistors. Apart from being noiseless, they don’t suffer from self-heating and normally offer a better matching and temperature drift.
  3. The capacitors decouple the input common mode from the rest of the signal chain common mode. This offers an advantage in terms of CMRR, PSRR, and THD.
  4. The capacitive PGA input common mode range may be rail to rail and beyond.

This capacitive architecture combines the benefits of an instrumentation amplifier, which is a really high input impedance, as the input impedance is a capacitor, with the benefits of capacitors over resistors as the gain element, increasing the dynamic range of the amplifier, not only in terms of signal swing but also noise efficiency.

A common solution to overcome the resistive PGA common mode limitation is to increase or shift the power rails or, alternatively, to re-center the sensor signal common mode, at the expenses of higher power consumption, supplies design complexity, additional external components and cost.

You will find Part 2 here: Integrated Capacitive PGAs in ADCs, Part 2: Practical Examples

0 comments on “Integrated Capacitive PGAs in ADCs, Part 1: Redefining Performance

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.