The scaling of CMOS technologies typically has a great impact on analog design. The most severe consequence is the reduction of the voltage supply. Imec and Renesas have managed to put a complete, high-performance SDR (Software Defined Radio) receiver into a 28nm CMOS process with a 0.9V power supply. The IC has everything except a PLL on a single monolithic chip. (See Figure 1.) This is an impressive integration of analog functionality.
(Image courtesy of imec and Renesas1 )
The vast majority of today's linear RF receivers are relatively power hungry and need to operate at higher supply voltages to get the specs needed for good performance, so the low-power/low-voltage supply used is a major coup in the quest for solutions that will extend the lifetime of battery-operated, portable systems.
The design team aptly chose an SDR architecture, which allows for versatility through reconfigurability and thus enables the IC to target such wide-bandwidth standards as LTE-Advanced (LTE-A) and 802.11ac.
This RF solution can handle a 0dBm blocker with a power dissipation of just 40mW. A 0.4 to 6GHz frequency range has been achieved with an impressive out-of-band third-order intercept point (OB-IIP3) of +5dBm.
The design team used some clever techniques to reach this type of performance at such a low power dissipation. The designers chose an alternative technique than that of noise-canceling and non-standard power supplies that previous designs have had to use.
Noise-canceling traditionally done in LNAs is as follows: The noise coming from a 50Ω impedance-matching resistor at the input of a wideband receiver is cancelled by measuring the current in that resistor and the voltage at the input port. The resistor's noise is cancelled using two gain paths, but the wanted signal appears in phase and is reinforced. (See Figure 2)
while the wanted signal is in phase and thus reinforced.
(Image courtesy ISSCC 2012, Session 4, RF Techniques, 4.13 )
Instead, the designers chose a split architecture of low-band (LB) and high-band (HB) RF paths to handle the frequency bands at 0.4 to 3GHz and 3GHz to 6GHz.
Of note is the fact that the designers have a complete linear SDR architecture on-chip except for the PLL, which is external to the receiver IC. For signals above 3GHz, a sub-40ps clock-width would be necessary. This would result in a fairly significant power dissipation on-chip — hence the decision to provide this function externally.
In reference paper 2, the designers note that “an 8-phase clock generator with high-frequency clock retiming drives the mixer switches without buffering.” The elimination of the typically power-hungry buffers “guarantees low enough blocker noise caused by reciprocal mixing, while keeping power consumption low,” according to the design team.
A transimpedance amplifier (TIA) drives a very efficient 11-bit, 250MSPS ADC whose architecture is a 2x interleaved, fully dynamic, pipelined SAR.
In the path below 3GHz, an inductor-less feedback LNA along with an 8-phase mixer helps to provide 3rd and 5th harmonic rejection (HR) and less than 2dB noise figure (NF) due to reduced noise folding from the image frequency.
As for the path above 3GHz, an inductor-based LNA needed to be used, but a 4-phase mixer was enough since HR is not necessary here (see reference 4).
The designers use two calibration schemes1 to get high IP2 and harmonic rejection as one scheme to provide high performance in the receiver.
(Image courtesy of imec and Renesas1 )
This design provides a similar NF, linearity, and blocker performance to the best SDRs to be found in literature. The differential receiver consumes better than 2x lower power and less die area at a greater than 1.5x lower supply, operating up to a more than 2x higher RF and IF frequency. See reference 1 for the full test results of performance.
I am expecting imec's partnership with Renesas and other suppliers to bring forth a bevy of low-power, high-performance radio ICs for the future of the “Internet of Things” with small RF devices becoming as ubiquitous as the clothing we wear. What uses do you anticipate for this technology?
- “A 0.9V Low-Power 0.4-6GHz Linear SDR Receiver in 28nm CMOS,” Jonathan Borremans, Barend van Liempd, Ewout Martens, Sungwoo Cha, Jan Craninckx
- “A 2.1 mW 11b 410 MS/s Dynamic Pipelined SAR ADC with Background Calibration in 28nm Digital CMOS,” Bob Verbruggen, Masao Iriguchi, Manuel de la Guia Solaz, Guy Glorieux, Kazuaki Deguchi, Badr Malki, Jan Craninckx
- “A blocker-tolerant wideband noise-cancelling receiver with a 2 dB noise figure,” David Murphy, Amr Hafez, Ahmad Mirzaei, Mohyee Mikhemar, Hooman Darabi, Mau-Chung Frank Chang, Asad Abidi
- “A 40 nm CMOS 0.4-6 GHz Receiver Resilient to Out-of-Band Blockers,” J. Borremans et al., J. Solid-State Circuits, Vol. 46, No. 7, pp 1659-1671, July 2011.