Last month, we discussed the various power supply inputs of a typical ADC. These include power supply inputs for optional input buffer circuits, the analog circuits, the digital circuits, and the output driver circuits.
With the sampling speeds of currently available ADCs and the many different voltage and clock domains inside a typical ADC, it is usually recommended to keep separation in the power supply inputs. By keeping the power supply inputs on separate domains, crosstalk between supplies can be minimized, and noise has a much harder time crossing between domains, where it could creep up and cause a problem with ADC performance. If it is not possible to keep them on separate domains, then at a minimum components such as ferrite beads can be used to give some isolation between supply domains. One method of driving the power supply inputs separately is by using low dropout (LDO) voltage regulators. An example is shown in Figure 1 below.
LDOs are typically the safest type of power supply and typically have the least risk in driving the power supply inputs to an ADC. Generally, LDOs offer very low noise and a high power supply rejection ratio (PSRR). The low dropout typically means that the input supply to the LDO can be as low as a few hundred millivolts above the LDO's output voltage. For example, the ADP1741 2A LDO can have as little as a 400 mV headroom (Vin must be 400 mV greater than Vout). For a typical supply rail of 1.8 V that one would encounter on an ADC, this means the efficiency of the LDO would be approximately Vout/Vin = 1.8/2.2 = 81.8%.
This is not inefficient by any means, but as we'll find in my upcoming blogs, there are more efficient devices we can use to drive the ADC power supply inputs. However, the efficiency of these other devices comes with a cost. As I mentioned, two of the main advantages of the LDO are the low noise and high PSRR. Other devices typically trade off noise for efficiency.
For the ADP1741, the output noise between 10 Hz and 100 kHz is typically 65 µVrms at an output voltage of 2.5 V. Let's look at an example of the effects of this contribution. In a 14-bit 250 MSPS ADC with an input full scale of 2.0 Vpp and an SNR of 70 dB, the noise floor is 20 nVrms/rt-Hz. In the first Nyquist zone, the ADC noise will be 223.61 µVrms (20 nVrms/rt-Hz * sqrt(250 MHz/2)). In this case, the ADP1741 output noise is much less than the ADC noise. In addition, the PSRR of the ADC (typically 60 dB) will further reduce the ADP1741 noise from 65 µVrms down to 65 nVrms (65 µVrms X 1 mV/V). This makes it easy to see why an LDO is such a nice option for driving the power supply inputs. It has virtually no impact on the ADC noise.
However, this does come with a price. One distinct disadvantage to using an LDO is the potential power dissipation. For example, let's look at the 14-bit ADC in the example above and assume it is a quad-channel device with a total power dissipation of 2 W, of which 1 W is needed for the AVDD supply. In this example, we are limited on the input supply to the LDO, and we have only a 6 V input available to drive the 1.8V AVDD supply. This means the ADP1741 would be required to dissipate an approximate power of (6 V – 1.8 V)/1800 mA = 2.33 W. This would push the maximum junction temperature (Tj) of the ADP1741 to TA + Pd X Θja = 85°C + (2.33 W X 42°C/W) = 183°C, which exceeds the LDO's maximum rating of 150°C.
This, of course, is an extreme example, but it illustrates the point of needing a low input voltage to the LDO. This can lead to using multiple LDOs to step down the voltage from a higher input supply rail down to a lower input supply rail required by the ADC. This provides a good lead into the next discussion. We'll take a look at this topology where multiple LDOs are used, and we'll examine some of the advantages and disadvantages.