After reading through the comments and having a few discussions with some of my coworkers, I thought it would be good to continue looking at the example I gave in my last blog (Interfacing to ADCs: Power Supplies, Part 2) where we looked using fewer LDOs and combining power supply rails on an ADC while maintaining isolation with ferrite beads. One very important item that I’ve left off thus far has been proper power supply decoupling. The focus has been more at a high level and looking at the topologies that can be used for ADC power supplies.
I want to take a moment to go back to that example and add in the decoupling. The size and value of the decoupling capacitors (shown as n capacitors in Figure 1) will depend on several factors, such as power supply voltage, frequency of operation, ADC power consumption, LDO characteristics, etc. There are many items to look at, but for the purpose of this discussion we will assume that the proper decoupling capacitors have been chosen. I’d ask that the reader keep in mind that it is always good design practice to decouple the power supply inputs to the ADC properly.
Let’s now take a look at a topology that will mitigate some of the power consumption issues we have looked at in the last few blogs. In many cases there is a higher voltage supply available in the system, but a lower supply voltage is required from the ADC. Many of the ADCs available today use a 1.8V power supply voltage. In many systems a higher supply voltage such as 6V or 12V is available (and could be higher in some cases). Let’s take a look at an example where a 6V power supply voltage is available and the ADC requires a 1.8V power supply input. For the purposes of this discussion we’ll focus mainly on the analog, digital, and driver supply inputs of the ADC. The input buffer supply is often a higher voltage such as 3.3V and is not a high current supply input, so the drop from 6V to 3.3V can be accomplished with a single LDO.
Let’s look at an example using the 14-bit 250MSPS dual channel AD9250. The typical total power consumption listed in the data sheet for the AD9250 is 711mW. This ADC has three power supply inputs which are the analog (AVDD), digital (DVDD), and driver (DRVDD) supplies. Let’s use the topology shown in Figure 1 and calculate the power consumption and junction temperatures. For this example, we will use two ADP1741 LDOs — one configured for a 3.3V output and the other configured for a 1.8V output — so that we produce the supply voltage needed as shown in Figure 1.
To begin, let’s look at the total current draw from the AD9250. Summing the current requirements from the three supplies, the total current requirement of the AD9250 is 255mA (IAVDD ) + 140mA (IDRVDD + IDVDD ) = 395mA. First let’s look at the case for the ADP1741 generating the 3.3V from the 6V supply input. In this case, the ADP1741 will be required to dissipate (6V – 3.3V) x 395mA = 1.067W. The means the maximum junction temperature Tj would be equal to TA + Pd x Θja = 85o C + 1.067W x 42o C/W = 129.79o C, which is less than the maximum rated junction temperature of 150o C for the ADP1741.
This is the larger of the two voltage drops on the supply rail so it means the second ADP1741 is ok as well, but let’s look at the calculations. We have the same current since the second ADP1741 as in the first ADP1741, which is 395mA. For the case of the second ADP1741, we have a voltage drop of 3.3V – 1.8V = 1.5V. Calculating the power dissipation, we arrive at (3.3V – 1.8V) x 395mA = 0.5925W. Now, calculating the maximum junction temperature we get 85o C + 0.5925W x 42o C/W = 109.89o C, which is once again less than the maximum rated junction temperature of the ADP1741. Assuming we have properly selected the ferrite beads and decoupling capacitors, we have arrived at a nicely functioning power supply for the ADC. Stay tuned as we continue to look at driving ADC power supplies.