# Interfacing to ADCs: Power Supplies, Part 5

In Interfacing to ADCs: Power Supplies, Part 4, we looked at using a DC/DC converter (switching regulator) in combination with an LDO to drive the power supply inputs to an ADC. What we found was that using the DC/DC converter to step down the input voltage for the LDO was a much more efficient way to drive the power supply inputs to an ADC. As a reminder, this topology is given in Figure 1 below. The input supply voltage is 5.0 V, which is stepped down to 2.5 V and then input to the LDO, which has a 1.8 V output for the ADC supply voltages.

Figure 1

Driving ADC Power Supply Inputs with a DC/DC Converter and LDO

I’d like to take a moment and expand a bit more on one of the topics I mentioned in this example previously, the potential spurs around the fundamental input tone to the ADC. The placement of these switching spurs will be dependent upon the switching frequency of the DC/DC converter and the input frequency of the ADC. The switching spurs will mix with the input signal and spurs will result at fIN — fSW and fIN + fSW (shown in Figure 2 below).

Figure 2

FFT of Digitized ADC Data with Switching Spurs

The good news is that with proper design, the amplitude of these spurs can be minimized and in many cases be lower than the harmonics or other spurs in the ADC spectrum making them a non-issue. So let’s look at some things to consider with regards to these spurs. Some of the common thought is that the LDO will “clean up” these switching spurs since the LDO has a high PSRR (power supply rejection ratio). In reality the PSRR is generally very good for an LDO up to a few hundred kilohertz.

Beyond a few hundred kilohertz, the PSRR generally begins to degrade fairly quickly. In general, a lot of the power supply noise in a system is typically in this frequency range so the LDO does a good job of sufficiently rejecting it. The PSRR of an ADC such as the AD9683 (which is the single channel version of the AD9250) shows better PSRR above 2 MHz as shown in Figure 3 below, which gives the PSRR up to 10 MHz. This leaves an area right around the switching frequency with less than desired combined PSRR.

Figure 3

The switching frequency of a DC/DC converter is typically 400-500 kHz up to 1-2 MHz. The switching spurs that are created at this rate may not be filtered entirely by the LDO and/or the ADC. These spurs could directly pass through and potentially show up in the output spectrum of the ADC as shown in Figure 2. That is, they will pass through unless the DC/DC converter layout and output filtering have been designed properly. This is why it is important to have a proper circuit design and layout as shown by Figures 4 and 5, which we also looked at last time.

Figure 4

Figure 5

By using proper circuit design with a good filter design on the output of the LDO as given by Figure 3, the switching spurs can be greatly reduced. This by itself is not all that it takes however, it is also important to pay attention to the layout. Just as with any high frequency or switching device, it is important to pay attention to current return paths to make sure there isn’t a potential for the switching noise to make its way into the ADC or other components that may also be on the same board. It is important to keep these current return paths very small. It is also important to keep them physically isolated from sensitive nodes in the design so the switching noise coupling is minimized.

As you can see, there are many aspects to consider, but that is what makes engineering so challenging and fun at the same time. Stay tuned as we look next time at driving the power supply inputs to an ADC directly from a DC/DC converter.