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Interleaving Spurs: Bandwidth Mismatches

By now you may be wondering how many more mismatches we have to look at when dealing with interleaved ADCs… well, we've finally arrive at the last one, bandwidth mismatch.

So far we've examined offset, gain, and timing mismatch. Now we'll look at what perhaps can be considered the most difficult mismatch to combat, which is the bandwidth mismatch between interleaved ADCs. As shown in Figure 1, the bandwidth mismatch has a gain and a phase/frequency component. This makes bandwidth mismatch more difficult because it contains components from two of the other mismatch parameters, gain and timing mismatch.

Figure 1 Bandwidth Mismatch

Figure 1 Bandwidth Mismatch

In the bandwidth mismatch, however, we see different gain values at different frequencies. In addition, the bandwidth has a timing component, which causes signals at different frequencies to have different delays through each converter. The best way to minimize the bandwidth mismatch is to have very good circuit design and layout practices that work to minimize the bandwidth mismatches between the ADCs. The better matched each ADC is, the less the resulting spur will be.

Because of the variation in gain and timing over frequency, any type of algorithm to try and calibrate for the errors would be extremely complex. This would likely increase circuit and area overhead too much to make the benefits of the calibration worthwhile. As it turns out, proper layout techniques can help to minimize this mismatch while properly accounting for the other mismatches (offset, gain, and timing) makes a significant impact on the interleaving spurs.

On my last several blogs we've looked at the various mismatches that cause issues when interleaving ADCs. As we take a look back over this discussion it is apparent that many of the mismatches have something in common. Three of the four produce a spur in the output spectrum at fS /2 ± fin . The offset mismatch spur can be easily identified since it alone resides at fS /2 and can be compensated fairly easily. The gain, timing, and bandwidth mismatches all produce a spur at fS /2 ± fin in the output spectrum so the question is how to identify the contribution of each. Figure 2 gives a quick visual guide to the process of identifying the sources of the spurs from the different mismatches of interleaved ADCs.

Figure 2 Interrelated Nature of Interleaving Mismatches

Figure 2 Interrelated Nature of Interleaving Mismatches

The offset mismatch creates a spur that is isolated at fS /2. This is relatively simple to located and identify. If looking purely at gain mismatch alone, it is a low frequency, or DC, type of mismatch. The gain component of the bandwidth mismatch can be separated from the gain mismatch by performing a gain measurement at low frequency near DC and then performing gain measurements at higher frequencies. The gain mismatch is not a function of frequency like the gain component of the bandwidth mismatch.

A similar approach is used for the timing mismatch. A measurement is performed at low frequency near DC and then subsequent measurements are performed at higher frequencies to separate the timing component of bandwidth mismatch from the timing mismatch.

So that sums up our discussion on the various mismatches that we encounter when interleaving ADCs. I trust that the discussion has been useful and we all now know a bit more about interleaving ADCs. Stay tuned as we start taking a look at some ways that we might try to calibrate for these mismatches. There are several good papers out there that offer some interesting approaches. Again, keep those questions coming and we'll see where things take us.

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9 comments on “Interleaving Spurs: Bandwidth Mismatches

  1. SunitaT
    August 31, 2013

    The bandwidth mismatch is more problematic because it contains components from two other mismatched parameters like gain and frequency component. The greatest way to lessen bandwidth mismatch to get a very decent circuit design and layout exercises that work to lessen bandwidth mismatches between the interleaved ADC.

  2. David Maciel Silva
    August 31, 2013

    In some situations this is not possible recourse but to use a uC, we solved this with greater ease because we have multiple AD channels available with a lower level of interference …

    But obviously this will depend on many factors, and especially the application.

  3. samicksha
    September 2, 2013

    Interesting Blog@Jonathan: Diagrams and content of your blog keeps up the good clarity but i am little more curious on what really you denote as Good circuit design..is it you want perfect timing matches without any delay or mismatch..

    The best way to minimize the bandwidth mismatch is to have very good circuit design and layout practices that work to minimize the bandwidth mismatches between the ADCs.

  4. jonharris0
    September 3, 2013

    Thanks for the great comments here all!  Indeed this is a mismatch that is quite difficult to handle.  My meaning was to make the circuit designs and the layouts as symmetric and matched as is possible to help minimize items that would affect the bandwidth of each channel.  This in my view is the most efficient way to combat bandwidth mismatch.  You'd need to pay careful attention first to the design to make sure each channel is designed as similar as possible, then make sure the layout is as matched as possible including not only the circuits but the routing as well.  The unfortunate things is that you still have process issues to battle as there are typically gradients across a wafer in terms of transistor beta and the like.  It still won't be perfect, but at least you know you've put your best foot forward.

  5. Per Lowenborg
    September 5, 2013

    Thank you for this mismatch error walk-through.

    If you are interested in seeing what digital mismatch error correction can achieve with bandwidth mismatch in terms of gain and phase-delay versus frequency, I can recommend to take a look at the following article I wrote recently for EDN T&M. You can find it at: 

    http://www.edn.com/design/test-and-measurement/4418920/Wideband-error-correction-elevates-time-interleaved-ADCs

  6. jonharris0
    September 9, 2013

    I believe another poster had linked to your article in a previous comment.  It is definitely an interesting read.  A different way to approach the errors.  One limitation I noted as I re-read the article was that it was limited to within a Nyquist band.  Several customers I've had experience with cross Nyquist boundaries these days especially with multi-band applications becoming more popular.  Thanks for the comment!

  7. Per Lowenborg
    September 10, 2013

    The right-hand part of Figure 5 shows the measured aliasing level in the system second Nyquist band, i.e. the third and fourth Nyquist band of the ADS5474 ADCs.

    It is on the second page.

  8. Brad_Albing
    September 21, 2013

    @Per – thanks for the heads-up and the link to your article on our sister site.

  9. Brad_Albing
    September 21, 2013

    @Per – any discussion of the higher Nyquist bands or zones is useful stuff. I may have to write a blog on this – unless you or Jonathan wants to.

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