Last time, we took a look at the offset mismatch that need to be considered with interleaved ADCs. Now, let's up the complexity a bit and look at gain mismatch.
I can see that the topic of interleaved ADCs has everyone's ears perked up. I am enjoying the interactions with you via the great comments and questions, so let's keep this going. Several questions have centered on calibration methods for the ADC mismatches. Before we dive into any type of potential calibration methods, let's continue to look at what mismatches there are. First of all, it is important to understand what we are dealing with. As a marketing friend of mine likes to say, “Let's continue to peel the onion back and see what we find.”
In the case of the offset mismatch, there was no need to apply an input signal to see the resultant spur in the output spectrum. The manifestation of the offset mismatch as a spur in the output spectrum is simply a result of the static DC offset on each ADC. The act of switching between the two ADCs produces a tone at fS /2 (for the case of two ADCs).
Now, let's take a look at the gain mismatch between interleaved ADCs. The image below shows the gain mismatch between two interleaved ADCs. In this case, a signal must be applied to the ADCs. There is no way to see the gain mismatch unless a signal is present and the gain mismatch can be measured. Unlike the spur resulting from the offset mismatch, the spur resulting from the gain mismatch has a frequency component. The gain mismatch will result in a spur in the output spectrum that is related to the input frequency, as well as the sampling rate, and will appear at fS /2±fin .
One method to minimize the spur caused by the gain mismatch is similar to the one we discussed last time for the offset mismatch. The gain of one ADC is chosen as the reference, and the gain of the other is set to match that value as closely as possible. The better the gain values are matched to each other, the smaller the spur will be in the output spectrum.
This raises the question that I know is on everyone's mind: how we might calibrate for the gain mismatch. There are a couple of ways to look at the gain mismatch. One way is to generate a signal (in system or on chip, for example) for calibration, so the gain mismatch can be observed and compensated. This would most likely require the system to be down while the calibration is performed.
Another way is to use the incoming signal in normal operation to perform the calibration. This is nice, since we don't have to take the system down — but it comes at the expense of a more complex algorithm and design for the compensation circuitry. The compensation method would have to be flexible enough to work with a wide range of possible input conditions. In addition, the response time for the calibration would limit performance for some period. But I digress; let's not get into too much detail before we finish looking at the different mismatches.
We now know about offset and gain mismatches we'll encounter when interleaving ADCs. We see that, when interleaving ADCs, two locations must be observed for spurs that result from mismatches in the ADCs. Now that we know about these two mismatches, we are halfway there.
There are still two more mismatches to consider when interleaving ADCs: timing and bandwidth mismatches. As we move along, we'll see how the complexity increases with each of these mismatches. As you're beginning to see, the advantages of interleaving do not come for free. We have several mismatches that we must consider carefully.
Don't forget that we'll also need to consider the analog input bandwidth of the ADCs. The input bandwidth must be sufficient for us to take advantage of all the extra Nyquist bandwidth that interleaving gives us. But we have much ground to cover before we get there. Stay tuned as we continue our discussion of interleaved ADCs and talk about the timing mismatch. Keep those questions and comments coming, as well.