Now things are getting interesting. We've been looking at where the interleaving spurs are located and have taken a look at the level of the spur produced from the offset mismatch. By doing some calculations we were able to see how big of a spur would result from offset mismatch between two interleaved ADCs. Just as we did when looking at the locations of the spurs, we'll take a similar path now. We had first looked at offset mismatch, so now let's dive into how we can calculate the level of the spur produced at f_{S} /2 Â± f_{in} due to the gain mismatch.

It's time again to put on our mathematician's hat for just a momentâ€¦ Don't worry though, we won't be wearing it for too much longer. We'll need it just for a while as we continue to look at some mismatch and dive into the gain mismatch spur.

So how do we know how big the spur from the gain mismatch is going to be? Let's take a look at Equation 1 below where V_{FS1} and V_{FS2} are the full scale peak-to-peak voltages of the two ADCs that we are interleaving.

**Equation 1**

Now, let's consider we have a typical gain mismatch between two 14-bit ADCs in a dual channel device. Typically this is about 1 percent of full scale for the nominal value. This means that ADC1 has a full-scale voltage of 2V_{P-P} that ADC2 would have a full-scale voltage of 1.98V_{P-P} . Substituting this in Equation 1 we get the following:

Wow, that is quite interesting! One percent of full-scale doesn't seem like much of a gain error, but it results in a fairly large offset spur of 46dBc. I doubt that there are many applications today for high speed ADCs that could tolerate this level of spur in the output spectrum. This would easily dominate the spurious free dynamic range (SFDR) specification for the interleaved ADCs. Most applications require an SFDR of at least 70dBc or better which means that 46dBc is much too high. Let's take a look at where we need to be in order to meet or exceed a 70dBc level. Below in Figure 1 the magnitude of the gain mismatch spur is shown with respect to the gain mismatch given in percent full scale.

**Figure 1**

This plot gives us some good information and some insight into what gain mismatch levels we can tolerate. In order to meet typical spurious requirements of 70 dBc, the gain mismatch must be less than 0.05% of full-scale for a 14-bit converter. This gives us an idea of how closely the gain between the two ADCs needs to be matched. It's pretty small.

However, as process technologies shrink and matching techniques improve it becomes easier to minimize the gain mismatch. On a device like the AD9286, the typical gain mismatch is about 0.05% of full scale, which places us right on the 70dBc specification we are looking for. If we can reduce the mismatch by another 0.025% then we can lower the gain mismatch spur down to 78dBc. If we can go further and reduce the mismatch down to 0.005% then we can lower the spur down to 92dBc.

This tells us that there is hope; we just need to figure out a good way to reduce the mismatch. This math hat is coming in handy. We can use it again next time as we look at calculating the level of the timing mismatch spur. Stay tuned and keep those comments and questions coming!

**Related posts:**

- Interleaving Spurs: Letâ€™s Look at the Math
- Interleaving Spurs: Bandwidth Mismatches
- Interleaving Spurs: Timing Mismatches
- Interleaving Spurs: Gain Mismatches
- Interleaving Spurs: Offset Mismatches
- More Thoughts on Interleaved ADCs
- Interleaved ADCs: The Basics
- LVDS Is Dead? Long Live LVDS & JESD204B

Spurious performance and Achievable resolution of ADCs are strongly connected to the supreme sampling occurrence of the device. Nowadays, in mid-2013, sample rates of commercially available 16-bit massive, single-core (non-added) ADCs are restricted to 250 MS/s though 14-bit ADCs could be found up to 400 MS/s.

In the equation above for the interleaving spur for the gain, inside the log formula should be [(1- 1.98/2)/2].Â Apologies for the error.Â Thanks to a coworker for pointing this out.

I don't think your coworker is quite correct. They are likely objecting the negative arguement of the log. If you use ABS of the log arguement, then the prose defining the full scale voltages and the equation symbology match. Otherwise I believe you need to specify that the lower fullscale voltage is used as VFS1 and the larger as VFS2 – which is the opposite of what the prose states. And the value is numerically what you show.

What bothers me is that if I set say VFS1 to 1.8 and VFS2 to 2, using your equation, and then reverse the roles letting VFS1 be 2 and VF2 be 1.8Â then even using the ABS function doesn't help as the values are ~ 1 dB different. Which bothers me that the dBc would be different depending on which converter I label as 1 or 2. So I am guessing that your comment about log arguement relates the defnition in the equation and that VFS1 is to be the lower fullscale voltage and VFS2 is to be the larger FS voltage. Regardless of which converter might be labels “1” or “2” say on a drawing.

So can you explain the proper interpretation or conditions for deriving the formula given so that the equation can be properly applied.

Â

THanks..