Now things are getting interesting. We've been looking at where the interleaving spurs are located and have taken a look at the level of the spur produced from the offset mismatch. By doing some calculations we were able to see how big of a spur would result from offset mismatch between two interleaved ADCs. Just as we did when looking at the locations of the spurs, we'll take a similar path now. We had first looked at offset mismatch, so now let's dive into how we can calculate the level of the spur produced at fS /2 ± fin due to the gain mismatch.
It's time again to put on our mathematician's hat for just a moment… Don't worry though, we won't be wearing it for too much longer. We'll need it just for a while as we continue to look at some mismatch and dive into the gain mismatch spur.
So how do we know how big the spur from the gain mismatch is going to be? Let's take a look at Equation 1 below where VFS1 and VFS2 are the full scale peak-to-peak voltages of the two ADCs that we are interleaving.
Now, let's consider we have a typical gain mismatch between two 14-bit ADCs in a dual channel device. Typically this is about 1 percent of full scale for the nominal value. This means that ADC1 has a full-scale voltage of 2VP-P that ADC2 would have a full-scale voltage of 1.98VP-P . Substituting this in Equation 1 we get the following:
Wow, that is quite interesting! One percent of full-scale doesn't seem like much of a gain error, but it results in a fairly large offset spur of 46dBc. I doubt that there are many applications today for high speed ADCs that could tolerate this level of spur in the output spectrum. This would easily dominate the spurious free dynamic range (SFDR) specification for the interleaved ADCs. Most applications require an SFDR of at least 70dBc or better which means that 46dBc is much too high. Let's take a look at where we need to be in order to meet or exceed a 70dBc level. Below in Figure 1 the magnitude of the gain mismatch spur is shown with respect to the gain mismatch given in percent full scale.
This plot gives us some good information and some insight into what gain mismatch levels we can tolerate. In order to meet typical spurious requirements of 70 dBc, the gain mismatch must be less than 0.05% of full-scale for a 14-bit converter. This gives us an idea of how closely the gain between the two ADCs needs to be matched. It's pretty small.
However, as process technologies shrink and matching techniques improve it becomes easier to minimize the gain mismatch. On a device like the AD9286, the typical gain mismatch is about 0.05% of full scale, which places us right on the 70dBc specification we are looking for. If we can reduce the mismatch by another 0.025% then we can lower the gain mismatch spur down to 78dBc. If we can go further and reduce the mismatch down to 0.005% then we can lower the spur down to 92dBc.
This tells us that there is hope; we just need to figure out a good way to reduce the mismatch. This math hat is coming in handy. We can use it again next time as we look at calculating the level of the timing mismatch spur. Stay tuned and keep those comments and questions coming!