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Interleaving Spurs: Offset Mismatches

As I read over the comments on my last few blogs about interleaving, it became apparent that this is an interesting topic for our readers. Some great questions were posed about interleaving, and up until now we've talked about the good things that interleaving brings. I appreciate these great comments and questions. These have made a good lead in to a discussion of the challenges that interleaving brings. As we all know, there is no such thing as a free lunch.

There are some challenges and things to look out for when interleaving ADCs. Imperfections associated with interleaving ADCs produce spurs in the output spectrum. These imperfections are basically mismatches between the two ADCs being interleaved. The spurs are produced by four basic mismatches: offset mismatch, gain mismatch, timing mismatch, and bandwidth mismatch. The offset mismatch between ADCs is probably the easiest of these to understand, so let's dive into that a bit further.

Each ADC that is interleaved will have an associated DC offset value. When the two ADCs are interleaved and samples are acquired back and forth between them, the sample DC offset changes. The image below gives an example of how each ADC has its own DC offset and how the interleaved output will effectively switch back and forth between offset values.

Offset mismatch.

Offset mismatch.

The output switches between these offset values at a rate of fS /2, which will result in a spur in the output spectrum located at fS /2. If you are interleaving more than two ADCs, the spur products appear at different locations, as shown in the table below. As you would imagine, the more ADCs that are interleaved, the more spurs they will produce.

Spur locations with respect to number of interleaved ADCs.

Spur locations with respect to number of interleaved ADCs.

Let's get back to the case of two interleaved ADCs. Since the mismatch itself does not have a frequency component and is only at DC, the frequency of the spur that appears in the output spectrum depends only on the sampling frequency and will always appear at a frequency of fS /2. The magnitude of the spur is dependent upon the magnitude of the offset mismatch between ADCs. A bigger mismatch will produce a larger spur.

To minimize the spur caused by the offset mismatch, it is not necessary to null the DC offset completely in each ADC. Doing this would filter out any DC content in the signal and would not work for systems using a zero IF architecture where the signal content is real and complex and includes data at DC. A more appropriate technique would be to match one ADC's offset to the other. One ADC's offset is chosen as the reference, and the other is set to match that value as closely as possible. The better matched the offset values are, the lower the resulting spur will be at fS /2. This compensation technique can be expanded and applied to cases where you have more than two interleaved ADCs.

That gives us an overview of the offset mismatches we'll encounter when interleaving ADCs. In an ideal world, we would have perfectly matched ADCs that would have no mismatches, but as I mentioned, we all know there is no such thing as a free lunch. We get lots of nice benefits from interleaving, but they don't come for free. We will continue to look at the different mismatches between interleaved ADCs in future posts.

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5 comments on “Interleaving Spurs: Offset Mismatches

  1. Dirceu
    July 12, 2013

    Jonathan,

      With ADC offset mismatches, a calibration procedures could help? Perhaps some kind of DC restore circuit (op. amp. or software based). I think in measuring devices, for example in the medical field: Unlike the ECG, an oximeter need the DC components of the signal.

  2. jonharris0
    July 12, 2013

    Hi Dirceu, yes, a calibration procedure would definitely help.  When doing the calibration you'd need to make sure not to remove the DC content as many applications use content around DC.  As I mentioned, one approach would be to just make the offset of each ADC equal so you don't affect the incoming DC content of the input signal.

  3. Davidled
    July 14, 2013

    I think that in most case, A/D converter chip is used to get A/D from VIN in the circuit. For example, let us say that two ADADC71 chips, 16 bit A/D converter, are used in parallel similar to “Offset mismatch” figure above. I am wondering how this circuit overcomes offset mismatch in this case.

  4. Brad_Albing
    July 15, 2013

    @JH – more details on auto-cal methods to remove (or match) DC offset in a future blog, perhaps….

  5. jonharris0
    July 15, 2013

    @DaeJ, thanks for the question.  The figure is intended just to show that the offset mismatch exists.  It is not necessarily a calibration circuit, sorry for the confusion on that.

    @B_Albing, thanks for the comment as well…that is something good to keep in mind.  I'm hoping to dive into a few more of the mismatches in upcoming blogs, but perhaps a good direction afterward may be to discuss some calibration methods…

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