# Interleaving Spurs: Timing Mismatches

So far we’ve looked offset and gain mismatch between interleaved ADCs. Once again, let’s up the complexity just a bit more and take a look at timing mismatch. There have been lots of great questions and comments related to the topic of interleaved ADCs, so let’s keep this thing going and continue with some great discussion.

Judging from the comments it seems there is a good bit of interest in calibrating for the various mismatches that exist between ADCs. I do hope to make it at least to a high-level discussion of that topic (high-level because the details can get pretty nasty pretty quickly), but first let’s take things one step at a time and continue to peel the onion one layer at a time. Besides, this is a blog which should be reasonably short and not too detail-ridden with the risk of making you terribly bored.

We must first understand what we are up against and define the problem before we set out to tackle a solution. Just as an architect draws up his plans before the builder pours the concrete for the foundation, we need to make sure we understand the interleaving spurs before we try to do any kind of calibration for them.

As with the case of the gain mismatch before, an input signal must be applied to see the resultant spur in the output spectrum. The timing mismatch has two components, group delay in the analog section of the ADC and clock skew. The analog circuitry within the ADC has an associated group delay, and the value can be different between the two ADCs.

In addition, there is clock skew that has an aperture uncertainty component in each of the ADCs and has a component related to the accuracy of the clock phases that are input to each converter. Figure 1 gives a visual representation of the mechanism and effects of the timing mismatches in the ADCs. What we find is quite interesting: The resultant spur is located at fS /2 ± fin . Does that sound familiar? It should, it is at exactly the same spot in the output spectrum as the spur resulting from the gain mismatch!

Figure 1

Timing mismatch.

Similar to the gain mismatch spur, the timing mismatch spur is also a function of the input frequency and the sample rate. On top of that, isn’t it nice that it appears at fS /2 ± fin , which is at the exact same location as the spur resulting from gain mismatch?

This is getting more fun by the minute, huh? The good news is that we can do some tests in order to tell how much each of the two mismatches contributes to the spur. Let’s hold onto that thought for now though. We’ll come back to that soon as we continue down on this path looking at interleaving. Let’s stay focused on the timing mismatch for now.

In order to minimize the spur caused by the timing mismatch, the group delay through the analog section of each converter needs to be properly matched with good circuit design techniques. In addition, the clock path designs need to be closely matched to minimize aperture uncertainty differences. Let’s not forget that the clock phase relationships need to be precisely controlled such that the two input clocks are as close to 180° apart as possible.

As with the other mismatches, the goal is to attempt to minimize the mechanisms that cause the timing mismatch. The better job done up front to control these mismatches, the easier the job will be to try to calibrate for them later.

As I mentioned earlier, let’s make sure we get a good set of plans to start with before we pour any of the foundation. We must also consider that we want to start with a good foundation when the time comes so that we have a nice firm place for our building to begin. This foundation begins with understanding all these mismatches so we know what we are getting ourselves into.

Stay tuned as we continue on in our discussion of interleaved ADCs and talk about bandwidth mismatch and some ways to distinguish the interleaving spur products. Keep those questions and comments coming as well.

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## 3 comments on “Interleaving Spurs: Timing Mismatches”

1. razvan.tataroiu
August 28, 2013

Somewhat off-topic, but related to high-performance ADC timing: I'm seeing aperture jitter specifications for high-speed ADCs in the 100fs area. I understand that in order to obtain specified SNR performance, a clock source with similarly low jitter specs is needed. However I find it very difficult to obtain such a clock source as an integrated module. Although various PLL-based clock generator ICs exist with exceptionally low additive jitter (and, related to this post, adjustable delay for each clock channel), they still require a stable low-frequency reference. Could you perhaps recommend such a clock source available as a module from a well-known distributor? Or is it that I have to design a discrete solution?

Thank you for your insight.

2. jonharris0
August 29, 2013

Razvan, this is a good question. Thanks for the comment. In order to obtain the true performance of the ADC, a low jitter clock source (~100fs) is needed.  As you mentioned, finding a clock source with this level of jitter is a little difficult.  You are also correct that a low jitter reference is usually required.  I am not aware of any modules that are out there that provide this low level of jitter.  Typically we use an input from the Rohde-Schwarz SMA100 signal generators to provide a low jitter (ala low phase noise) input.  Also, Wenzel makes some nice oscillators that have very low phase noise as well and can be used to clock high speed ADCs.  I'm not sure however if they offer anything that would be surface mount.  The ones that I use are powered from a 15V supply, have SMA connector outputs, and are about 2″x2″ square.  Do also keep in mind that the overall SNR of the signal chain is also affected by the driver amplifier noise and gain as well as the AAF in front of the ADC.

3. jonharris0
August 29, 2013

Actually a discussion on the different things that impact the ADC noise sounds like a good idea for a blog… 🙂  I may take a slight detour and address that topic on a blog soon.

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