Over time in the semiconductor industry, several technology shifts have required EDA tool vendors to develop new solutions. We are once again at such a shifting point in the traditional methods of design.
Custom layout tools are occupying an increased percentage of design tool budgets as process nodes gets smaller and more complex. Digital tools have become almost “push button,” high-value commodities, and analog tools are increasingly having new high-value specialized functions.
Why is this shift occurring now? Legacy custom layout tools, which are still mostly manual, are now being updated to address FinFETs, but these toolsets were originally largely designed for 90/65 nm, so this update process gets increasingly difficult. As geometries fall, we see a kind of Moore’s Law for process rules whereby the combination of dos and don’ts seems to double with every new node. Although it is still feasible to code many of these rules into the tools, the additional effort to do so is becoming exponential with each node.
Where sparse pieces of automation do exist in today's custom tools, this problem gets even more exaggerated. Tool architectures and algorithms need to accommodate double, triple, or quadruple patterning, substantially increasing the effort of managing all of the combinations of geometries and layout variations required to adhere to DRC rules at 16/14 nm and beyond. These tools were never developed with these new requirements in mind, and continuous rewrites will not be enough to solve the problems posed by smaller geometries. In addition, existing reference flows have too many repetitive, time-consuming, linear steps.
The typical flow at smaller process nodes requires a DRC/color check at each stage of the layout — before placement, post placement, post routing, etc. This is obviously not an optimal flow; it’s more a reflection of the inability of the tools on the market to address such things as double patterning in one iteration. Naturally, these inefficiencies introduce significant delays into the design cycle.
We anticipate that new approaches will have to be introduced to enable highly optimized layout. The evolution of the FinFET era necessitates new smart tools that can “think” for themselves and anticipate the required behavior (DRC-correct APR) given a set of inputs (DRC and process rules). Tools will be required that can generate layout, undertake all placement permutations, complete routing for each permutation, and ensure that it is DRC-correct — all in one iteration.
Digital cell-based tools work on a very structured basis, which is why they can be optimized to be able to place millions of standard cells in highly structured rows/areas. Custom analog tools, on the other hand, face more abstract challenges with the placement of devices in a given area, especially unevenly shaped areas. They have to produce optimized layout, otherwise analog designers will not use them, and at 16/14 nm and below, the layout is completely tied to simulation — you can’t run simulation until you have a layout that is feasible.
In the past, the level of automation applied to analog design has never approached the level enjoyed by digital designers. This is where the shift is going to occur. As the challenges of layout become harder, the necessity for automation in custom analog tools will provide the most significant increases in productivity. Custom design tools will simply have to catch up with digital, and they will have new high-value specialized functions that will begin to represent a growing percentage of the value-add in chip design.