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JESD204B serial interface spec outperforms parallel formats

As the sample rate and resolution of today’s data converters increase, new high-density techniques for the digital data interface are being developed to cope with the large number of signals and high data transmission rates. 

High-speed serial interfaces offer numerous advantages over traditional parallel interfaces. But they can be challenging to implement for even the most proficient designers. While many system developers and designers acknowledge the enormous potential value they perceive increased risk and become reluctant to adopt the technology — even though existing solutions in many cases are more expensive and need more real estate and power.

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The benefits of these new interfaces are significant. A high-speed serial interface offers a significant reduction in the number of data and clock signals. This translates into fewer I/O pins, less PCB routing, and relaxed physical design constraints. In addition to these obvious benefits are system-level advantages.  

For instance, a hybrid fiber/coax network consists of hundreds of remote sites that convert data from coax to fiber and send it back to one central office. At each remote site, an ADC (analog-to-digital converter) digitizes signals from the coaxial cable. The ADC outputs are serialized and then broadcast over fiber via an optical transmitter. This can be implemented with a traditional (parallel) ADC — and some designers are doing so. But the design requires an additional element between the ADC and fiber optic transmitter to serialize the data, which is often expensive and space consuming.

Now, there is an alternative. Using an ADC with JESD204B-complaint high-speed serial outputs, designers can remove the dedicated serializing device, reducing the transmitter’s size and power consumption. This is possible because JESD204B data can be directly broadcast over fiber. In many cases, adopting a device with a new standard would be perceived as risky, but this simplified architecture can be prototyped and demonstrated using standard off-the-shelf evaluation kits of the JESD204B ADC and fiber-optic transmitter, no additional encoding, level translating, or serializing operations are required.

Benefits of the JESD204B standard

JESD204, a high-speed serial interface standard for data converters was initially introduced in 2006. It has evolved through three generations, JESD204, JESD204A, and JESD204B, with each revision enhancing the prior version. 

Two features critical to adoption in the communications and multichannel ADC markets were included in the B version.  First, JESD204B provides deterministic latency in mapping from the convert clock to the serial data output, allowing consistent data latency after every reset.  Second the B version of the standard increases the maximum data rate, providing for efficient use of fewer I/O resources.

For instance, the B standard allows a dual 14-bit 250Msps ADCs to use only one serial lane per channel.  Devices restricted to the ‘A’ version data rates would require two lanes per channel, doubling the I/O resources required. While the latency uncertainty and low data rates of the A standard impeded wide JESD204 adoption, the B standard will accelerate this important step forward, beginning in communications and/or multi-channel converter applications.

Simplifying the system architecture

Since these leading edge ADC’s perform the serializer operation, it is now possible to eliminate dedicated serializing devices from some system designs, reducing space, power, and cost. Start with the hybrid fiber/coax transmitter described above.

Traditionally, this system consists of an ADC, connected to an FPGA, connected to a fiber optic transmitter. The FPGA packetizes and serializes the data from a parallel output ADC. But using ADCs with JESD204B outputs, it is possible to remove the FPGA and connect the ADC output directly to the fiber optic transmitter. This removes cost and power from what is often a remote site, and shrinks the entire assembly.  

Similarly, consider a radar system that must transmit signals roughly 100 meters from an array of densely spaced receiving elements to a centralized DSP. Each element’s physical dimensions are constrained by the antenna design. This requires a very small form factor for each element's receive chain, typically including a filter, amplifier, ADC, and transmitter. Typical ADC outputs (LVDS/CMOS) can't be transmitted more than a few feet at most. This means that the outputs must be converted in some way in order to transmit them longer distances. Fiber optics are the obvious solution for transmitting digital data long distances, as long as the ADC data can be serialized and converted to optical — within the space constraints.  

In current implementations of both systems, the multi-gigabit serializing function is typically performed by a relatively high end FPGA. Moving the FPGA from the front end of designs and enlisting the JESD204B ADCs presents clear benefits. For a system such as a cable transmitter, for example, the FPGA is removed from each of the remote transmitting sites – saving cost and power — because the transmitter no longer requires it. For a radar system, to note another example, moving the FPGA from the space-constrained ‘front’ of the design to the more flexible ‘back-end’ is the only way to lay out the entire receive chain, from RF to digital to optical, within limited space allowed. (In both of these applications, FPGAs are required on the receiving end of the system and remain a vital part of the design.)

The alternative

Intersil has used its family of 12- to 16-bit JESD204B ADCs to develop a reference design that brings these reduced size, cost and power benefits to users. Using Avago fiber optic transceiver evaluation boards, several transmitting options have been demonstrated including the following: two-channel 14-bit ADC using two fibers; two-channel 12-bit ADC using one fiber; and one-channel 14- and 16-bit ADCs using two fibers. To receive and analyze the data, Intersil’s Xilinx Virtex-5 based JESD204B receiver reference design is used.  Please refer to Figure 1 for a sample block diagram of this system.

Among the kinds of designs that can benefit are these:

  • Cable Digital Return, Radio-over-Fiber, Antenna Array Processing: data is digitized, serialized, and then transmitted over a fiber cable.  JESD204B high speed ADCs can eliminate the need for a dedicated serializer function (eliminates or cost-reduces the FPGA).
  • Communications Infrastructure: Base-stations and remote radioheads often require multiple receivers.  Using a serial interface from ADC to FPGA simplifies the physical design, as long as the high-speed serial connection offers a constant latency.  JESD204B ADCs provide the serial connection and solves the problem of uncertain latency.
  • General Purpose I/O & Digitizer Modules: modular I/O cards are often used in a mix-and-match approach where an I/O card plugs into a data collection board.  These are often limited by the number of pins in the connector.  I/O devices using high-speed serial interfaces allow for a higher number of I/O channels.

The optical transmission of JESD204B ADC outputs can be accomplished using off-the-shelf fiber optic evaluation components and Intersil’s JESD204B ADC evaluation platform.  Referring to Figure 1 , one implementation that has been demonstrated to be effective digitizes two inputs using the ISLA222S, a 2-channel, 12-bit 150MSPS ADC with one serial output.  

The serial output of the ADC drives the TX input of an Avago fiber optic transceiver evaluation board. The fiber optic transceiver converts the 4.5 Gbps electrical data stream to optical and transmits it over the fiber to a second Avago fiber optic transceiver, which converts it back to electrical.  The transceiver’s RX output is wired to Intersil’s JESD204B motherboard where the data is de-serialized and displayed using Intersil’s JESD204B receiver reference design.

While high-speed serial interfaces are known to offer significant advantages, in the minds of many designers, they still come with implementation risks that are perceived to be high. But the standardization of the interface, in fact, reduces the adoption risk. 

As demonstrated here, devices that can support the JESD204B interface, even from varied suppliers such as Intersil, Avago and Xilinx can be quickly connected together to realize the immense benefits offered by high speed serial interconnect.


Click on image to enlarge.

Figure 1. Block Diagram with ISLA222S driving the TX input of an Avago fiber optic transceiver evaluation board.

Edward Kohler is Senior Strategic Marketing Manager for High Speed Data Converters at Intersil Corporation. He has worked in high-speed ADC design and marketing for eight years. He earned his BSEE degree from Michigan Technological University, his MSEE degree from the University of Michigan, and his MBA degree from Yale University.

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