Advanced short-geometry CMOS processes are subject to aging that causes major reliability issues, degrading the performance of integrated circuits over time. Two of the most problematic effects causing aging are hot carrier injection (HCI) and negative bias temperature instability (NBTI). Below 90 nm, consideration of the effects of HCI and NBTI is becoming mandatory for design flows targeting quality and reliability.
This article describes the industrial challenges associated with accurate modeling of aging problems, with a particular emphasis on NBTI. Particularly, a tight relation exists between design and reliability issues, and state-of-the-art simulation flows can help designers address these issues to create more reliable designs. The article also includes 13 references.
It is presented in three parts, as pdf files (no registration required), as follows:
Part 1 : Aging mechanisms in advanced processes; Investigating effects of NBTI and/or HCI on PMOS devices; DC stress, AC stress, and recovery: click here.
Part 2 : Reliability simulation; Joint design–reliability simulation flows; Cost of aging simulation; Statistical aging: will be posted December 21, 2009.
Part 3 : Benefits of a joint design–reliability flow; IP protection; Importance of flexible model definitions: will be posted December 28, 2009.
About the Authors
Cyril Desclèves is a product marketing manager for the Mentor Graphics Deep Submicron division (DSM), in charge of the analog and mixed-signal verification solutions.
Mark Hagan is senior manager of engineering services for Vitesse Semiconductor. He is responsible for a multitude of mixed-signal design areas including front end reliability modeling, with an overall expertise in ESD/latch-up modeling/implementation along with chip level integration in submicron processes.
Wenping Wang is a member of the technical staff also with Vitesse Semiconductor. She is responsible for front-end reliability modeling and implementation in regards to NBTI and HCI.