Just Add a Transistor: The 4-20 mA Current Loop

You know the “just add a transistor” drill by now: a performance or functionality requirement comes up that you can’t support entirely using the blocks built into your favorite mixed-signal system-on-chip device. (It is your favorite one, right? If not, tell me why and I’ll see what I can do.)

So here’s another of those old-school industrial sensing applications where deploying a three-legged friend makes sense. It’s the good old 4-20 mA loop. Originally just for analog signals, it is now often used with a superimposed AC communication layer called HART. The approach shown here is compatible with both uses.

Basics of the 4-20 mA loop
Three items are connected in series in a 4-20 mA loop connection, shown in Figure 1: the sensor, a power supply, and a load resistor. The power supply typically provides 24 V DC; it only needs to be of modest quality. The internal electronics in such sensors operates in a controlled-current mode and ensures that the current flowing in the loop reflects the desired sensed signal. Finally, the load resistor drops a voltage proportional to the loop current, and this voltage is measured by the receiving end of the system, to determine the sensed parameter.

The voltage that the sensor “sees” varies quite a lot due to the voltage drop in the load resistor and the connecting cable (which can be of considerable length in a large industrial plant) and also due to regulation issues in the main power supply. It can range up to 28 V and down to around 9 V.

Some robust and reliable means of monitoring and regulating the current flowing in the loop is required. The main complication here is that this current must include all the operational current of the sensor element and its support circuitry, as well as the current being tweaked by the interface in order to set the correct overall loop current. It’s topologically quite difficult to persuade both the external loop current and the circuit’s operational current through a local sense resistor while maintaining both ends of that resistor at voltages within an acceptable range for a PSoC — or any other single-supply signal conditioning circuit, for that matter.

The solution…
…is to permit the voltage at one end of the sense resistor, through which the loop current flows, to go outside the permissible range for the active device used — but sneakily use a resistor to turn it into a current flowing out from a device pin that’s held at a valid voltage. Let’s see how that works. Look again at Figure 1.

Figure 1

A 4-20 mA loop interface built round your favorite SoC.

A 4-20 mA loop interface built round your favorite SoC.

The block doing the heavy lifting here is the op amp. Its inverting input is hard connected to local Vss (the ground potential of the sensor circuitry itself, a point that is defined locally for the sensor, not imposed upon it from outside). In the circuit shown, it will do what’s needed at its output in order to ensure that the voltage at the non-inverting input gets to that value, too.

The amplifier’s output drives the base of the external transistor, whose emitter is also hard connected to local Vss. The transistor’s collector is connected to the positive loop connection terminal, and the negative loop connector returns to the emitter through a low-value resistor R_1 of value RSENSE acting as the local current sense resistance. Here RSENSE is set to 47 ohms.

Driving the transistor’s base positive with respect to Vss will turn it on, and this will allow current to flow in the external loop that, if the transistor were to be driven on hard enough, is only limited by the resistances in that loop. But we can build a handy negative feedback loop around this that can hold the current in the loop at some value of our choosing. How does this part work?

The secret is the connection, through a resistor R_2 of value RF (here 4.7 kohm), of the negative loop connection terminal back to the non-inverting input of the amplifier. If we just make this connection, the current in the loop will be forced to be the minimum possible value, set only by the inherent current consumption of the circuitry. That’s because if significant current were to start flowing in the loop, out of the emitter and through that resistor, the negative loop connection terminal, and therefore the input of the amplifier, would start to go negative of Vss. The op amp, whose inputs will function fine at voltages right around Vss (because our favorite SoC has rail-to-rail input capability), will resist that happening by forcing the base voltage of the transistor in a negative direction. This will keep happening until the transistor has turned off. The system driving the loop now just sees the current consumption of the circuitry itself (flowing into the regulator).

Now consider what happens if we dump a little current into that feedback resistor, let’s say by connecting the output of a sourcing IDAC (a DAC with a current output) to the non-inverting input of the amplifier where the resistor also attaches.

The amplifier is always going to want to do whatever it can to hold its non-inverting input very close to local Vss. But now there is current flowing in that feedback resistor, and in order for its “top” end to be at Vss, its “bottom” end must now be negative of Vssa by IDACRF. If this is the case, the current flowing in the sense resistor must be IDACRF/RSENSE. By changing the value of IDAC we change the current in the sense resistor — and therefore in the external loop.

Note that because the “top” end of the sense resistor is at Vss, all the supply current consumed by the entire sensor and PSoC also flows into it, so the transistor only has to make up the difference between the circuit consumption and the value now required to balance out the voltage dropped across the feedback resistor.

In the figure, the ratio between R_2 and R_1 is 100:1, so an adjustment range of 255 uA from the IDAC translates to a loop current control range of 25.5 mA.

All the time, the net that connects the IDAC output, the feedback resistor, and the amplifier’s non-inverting input (through a Kelvin connection that eliminates the risk of unwanted internal voltage drop across routing resistance) stays right at Vss, so the PSoC doesn’t have to manage any negative voltages it can’t handle.

A sensor built around such a SoC is highly likely to be a “smart” sensor communicating digitally with a HART-interfaced sensor hub. HART is a common protocol for interfacing with modern loop-powered sensors. This approach is particularly common when modern sensors need to be incorporated incrementally in existing industrial 4-20 mA loop infrastructures. The data sent to the IDAC can represent two elements: a static bias (or an analog representation of the sensed parameter — I’ll leave it up to you to figure out how to add some extra analog current into the mix); and a signal modulation corresponding to the FSK physical layer used by the HART system.

In our favorite SoC, DMA is the most likely method through which the data representing offset plus HART signal is transferred to the DAC. The 8-bit resolution of the IDAC might give cause for concern that spurious high-frequency signals may be imposed on the loop current. If this is thought to be a problem, a small capacitor, or series RC network (a small series resistance may improve loop stability), can be included across R_2. HART reception is not covered here; ways of fitting it onto any PSoC architecture can be (and have been!) devised.

So there you have it: yet another way in which our three-legged friends can add a real zip to a SoC circuit. By the way, the drawing in Figure 1 was done in Creator, the free tool that’s used to create the entire PSoC project, so you can smoothly document the entire thing. OK, promotion!

8 comments on “Just Add a Transistor: The 4-20 mA Current Loop

  1. antedeluvian
    July 18, 2014


    Great article. One of the problems of this configuration, especially for novices of the technique, is to try and get it working. It is difficult to measure anything when it isn't working, because it isn't working.

    Also developing it with an emulator is also problematic because the current consumption of the micro/emulator is not normally consistent with the standalone application.

    But the biggest problem I found was the current needs at startup. I built this system several years ago (albeit with an external amplifier). I tried the  PSoC1 and then a Microchip part. In both cases when running on an emulator the system worked. But at power up the current requirements were strangled by the current limiting of the system and they wouldn't start. All this is guesswork because it just didn't work and you can't use the emulator to find out what was happening. I did get the MSP430 to work though.

    I look forward to trying it out on a PSoc4/5

  2. Davidled
    July 18, 2014

    I am wondering whether cap or resistor might be required between voltage regulator and transistor in serial and parallel pattern to avoid the abrupt voltage behavior and zener diode might protect transistor due to the overvoltage.

  3. kendallcp
    July 18, 2014

    Good point.  A certain measure of protection would be routine here – a TVS, a fuse/PTC and a spark gap in the trackwork, to guard against extreme abuse. The transistor itself can be as robust as you like.  The regulator either needs to have a high maximum input voltage or a predictable input voltage limiting scheme – none of your fragile little LDOs – low dropout isn't a selection requirement here.

  4. samicksha
    July 19, 2014

    I guess in operations such as the over air television broadcasting, is better achieved in vacuum tubes due to its better electron mobility in a vacuum

  5. green_is_now
    July 23, 2014

    This is a many wire 4-20ma configuration, two independent power supplies or an op amp and a current source that can span the whole dynamic voltage range needed for 4-20ma range span, including over temp.


    What is missing from the sketch, for a clean schematic is the op amp and IDAC power rails. These MUST not get very close, including any output loss if not R2R to the rails of the power supply minus the IR on the sense resistor!

    Don't forget the changing voltage caused by the sense resistor!

    The additional blocks do not provide error reduction, just a selectable digital step response.

    I once designed a 2 wire calibratable, temperature compensated 4-20ma transducer within a 0.1 error band over 100 degree temperature range, without an MCU.

    All currents must go through the 4-20ma loop in a 2 wire 4-20.

    This is called one wire in other technology forms.


    this is because there is one single current in series for everything.

    4-20 mA loop allow for your transducer and your sense resistor and voltage translation of that current sense resitor to be in different locations, with different grounds potentially if 3 wire or more.

    2 wire eliminates this common mode error and failure modes.

    But they are not easy to design, even my design was an improvement to a timeless design that was from radio men of another era.

  6. kendallcp
    July 23, 2014

    Thanks for that!  I should perhaps have made stronger mention that the demands on the IDAC and the opamp are really quite lenient.  Only the voltage regulator input and the collector of the just-added transistor see the big voltage between the incoming wires.  The PSoC can work happily at 3.3 V supply from the regulator, or even lower if it's important.  The IDAC's output is pinned at the local Vssa value, as are both opamp inputs.  The opamp output only gets up to a Vbe above Vssa. None of the voltages get anywhere near a reasonable supply voltage.

    So if you really wanted to, and had a suitable regulator, you could run the loop of a 56 V telecom supply, or virtually any DC supply for that matter.  All the current that flows 'into' the circuit through the upper wire comes 'out of' the lower wire – whether it comes out of the transistor emitter, the reference pin of the regulator or the Vssa pin of the PSoC.  The loop will just regulate the sum of all of those currents, by appropriately modulating the transistor drive.

  7. green_is_now
    July 23, 2014

    The higher the voltage the more headroom for the series drops.

    thats why almost all are 28 volt inputs when a 5v output IR drop swing is needed for the ADC measurement. (1-4v here)

    Dropping IR measurement to 0.5 to 2.5 helps allow a 15 volt version, and so on.

    But as the headroom grows so does the voltage potential that when added to the unwanted common mode can leave voltage rail compliance zones. When your grounds get hammered with a ground bounce from different locations the op amp and IDAC rails ability to absorb this becomes important.

    3 or4 wire with the same star ground is preffered if more than two wire is used. 

    The wires can be induced anyway with or without current flowing, so this is not perfectly bullet proof.

    Always enjoy your articles, the filter wizard series were classics, fun and refence material all rolled into one.


  8. green_is_now
    July 23, 2014

    Tweaking a feedbackloop reminds me of venebles stuff for testing power supply loops.

    The resistor ratio counters the high gains available when “in the loop”.

    This could be used to modulate the HART signal onto the 4-20Ma signal if a signal was added in addition to the IDAC.

    Say a pressure sensor output analog signal.

    depending on the signal output a 1 to 127 Amplitude step modulation is possible.

    Balanced symetric modulation required to not offset base DC-LP signal. So above offsets must be offset with below offset from IDAC, this limits the levels allowed, with a maximum of 128 QAM at center point,12ma.

    We can call this Freeway Accessable  Remote Transmission or FART.

    Oh crap i think this is patentable.

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