You know the “just add a transistor” drill by now: a performance or functionality requirement comes up that you can’t support entirely using the blocks built into your favorite mixed-signal system-on-chip device. (It is your favorite one, right? If not, tell me why and I’ll see what I can do.)
So here’s another of those old-school industrial sensing applications where deploying a three-legged friend makes sense. It’s the good old 4-20 mA loop. Originally just for analog signals, it is now often used with a superimposed AC communication layer called HART. The approach shown here is compatible with both uses.
Basics of the 4-20 mA loop
Three items are connected in series in a 4-20 mA loop connection, shown in Figure 1: the sensor, a power supply, and a load resistor. The power supply typically provides 24 V DC; it only needs to be of modest quality. The internal electronics in such sensors operates in a controlled-current mode and ensures that the current flowing in the loop reflects the desired sensed signal. Finally, the load resistor drops a voltage proportional to the loop current, and this voltage is measured by the receiving end of the system, to determine the sensed parameter.
The voltage that the sensor “sees” varies quite a lot due to the voltage drop in the load resistor and the connecting cable (which can be of considerable length in a large industrial plant) and also due to regulation issues in the main power supply. It can range up to 28 V and down to around 9 V.
Some robust and reliable means of monitoring and regulating the current flowing in the loop is required. The main complication here is that this current must include all the operational current of the sensor element and its support circuitry, as well as the current being tweaked by the interface in order to set the correct overall loop current. It’s topologically quite difficult to persuade both the external loop current and the circuit’s operational current through a local sense resistor while maintaining both ends of that resistor at voltages within an acceptable range for a PSoC — or any other single-supply signal conditioning circuit, for that matter.
…is to permit the voltage at one end of the sense resistor, through which the loop current flows, to go outside the permissible range for the active device used — but sneakily use a resistor to turn it into a current flowing out from a device pin that’s held at a valid voltage. Let’s see how that works. Look again at Figure 1.
The block doing the heavy lifting here is the op amp. Its inverting input is hard connected to local Vss (the ground potential of the sensor circuitry itself, a point that is defined locally for the sensor, not imposed upon it from outside). In the circuit shown, it will do what’s needed at its output in order to ensure that the voltage at the non-inverting input gets to that value, too.
The amplifier’s output drives the base of the external transistor, whose emitter is also hard connected to local Vss. The transistor’s collector is connected to the positive loop connection terminal, and the negative loop connector returns to the emitter through a low-value resistor R_1 of value RSENSE acting as the local current sense resistance. Here RSENSE is set to 47 ohms.
Driving the transistor’s base positive with respect to Vss will turn it on, and this will allow current to flow in the external loop that, if the transistor were to be driven on hard enough, is only limited by the resistances in that loop. But we can build a handy negative feedback loop around this that can hold the current in the loop at some value of our choosing. How does this part work?
The secret is the connection, through a resistor R_2 of value RF (here 4.7 kohm), of the negative loop connection terminal back to the non-inverting input of the amplifier. If we just make this connection, the current in the loop will be forced to be the minimum possible value, set only by the inherent current consumption of the circuitry. That’s because if significant current were to start flowing in the loop, out of the emitter and through that resistor, the negative loop connection terminal, and therefore the input of the amplifier, would start to go negative of Vss. The op amp, whose inputs will function fine at voltages right around Vss (because our favorite SoC has rail-to-rail input capability), will resist that happening by forcing the base voltage of the transistor in a negative direction. This will keep happening until the transistor has turned off. The system driving the loop now just sees the current consumption of the circuitry itself (flowing into the regulator).
Now consider what happens if we dump a little current into that feedback resistor, let’s say by connecting the output of a sourcing IDAC (a DAC with a current output) to the non-inverting input of the amplifier where the resistor also attaches.
The amplifier is always going to want to do whatever it can to hold its non-inverting input very close to local Vss. But now there is current flowing in that feedback resistor, and in order for its “top” end to be at Vss, its “bottom” end must now be negative of Vssa by IDACRF. If this is the case, the current flowing in the sense resistor must be IDACRF/RSENSE. By changing the value of IDAC we change the current in the sense resistor — and therefore in the external loop.
Note that because the “top” end of the sense resistor is at Vss, all the supply current consumed by the entire sensor and PSoC also flows into it, so the transistor only has to make up the difference between the circuit consumption and the value now required to balance out the voltage dropped across the feedback resistor.
In the figure, the ratio between R_2 and R_1 is 100:1, so an adjustment range of 255 uA from the IDAC translates to a loop current control range of 25.5 mA.
All the time, the net that connects the IDAC output, the feedback resistor, and the amplifier’s non-inverting input (through a Kelvin connection that eliminates the risk of unwanted internal voltage drop across routing resistance) stays right at Vss, so the PSoC doesn’t have to manage any negative voltages it can’t handle.
A sensor built around such a SoC is highly likely to be a “smart” sensor communicating digitally with a HART-interfaced sensor hub. HART is a common protocol for interfacing with modern loop-powered sensors. This approach is particularly common when modern sensors need to be incorporated incrementally in existing industrial 4-20 mA loop infrastructures. The data sent to the IDAC can represent two elements: a static bias (or an analog representation of the sensed parameter — I’ll leave it up to you to figure out how to add some extra analog current into the mix); and a signal modulation corresponding to the FSK physical layer used by the HART system.
In our favorite SoC, DMA is the most likely method through which the data representing offset plus HART signal is transferred to the DAC. The 8-bit resolution of the IDAC might give cause for concern that spurious high-frequency signals may be imposed on the loop current. If this is thought to be a problem, a small capacitor, or series RC network (a small series resistance may improve loop stability), can be included across R_2. HART reception is not covered here; ways of fitting it onto any PSoC architecture can be (and have been!) devised.
So there you have it: yet another way in which our three-legged friends can add a real zip to a SoC circuit. By the way, the drawing in Figure 1 was done in Creator, the free tool that’s used to create the entire PSoC project, so you can smoothly document the entire thing. OK, promotion!