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Key Considerations for Multiplexed Data-Acquisition Systems

Multiplexing allows the use of fewer ADCs per system, offering significant savings in power, size, and cost. Successive-approximation ADCs — often called SAR ADCs for their successive-approximation register — have low latency, making them popular in multiplexed systems that demand fast response to a full-scale input step (worst case) without any settling time issue. Easy to use, SAR ADCs offer low power and small size.

This article focuses on the key design considerations, performance results and application challenges associated with multiplexed data-acquisition systems using high-performance precision SAR ADCs.

When the multiplexer input channel is switched, the ADC driver amplifier must settle a large voltage step within the specified sample period. The input can change from negative full-scale to positive full-scale, or vice versa, so a large input voltage step can be created in a small time. The amplifier must have a wide signal bandwidth and fast settling time to handle this step. In addition, nonlinear effects appear as a result of slew rate or output current limitations.

Also, the driver amplifier must settle the kickback caused by charge rebalancing on the SAR ADC input at the start of the acquisition period. This could become the bottleneck in settling the inputs in multiplexed system. Settling time issues can be reduced by lowering the throughput rate of the ADC, which provides longer acquisition time and allows the amplifier sufficient time to settle to the required accuracy.

The timing diagram in Figure 1 shows how to optimize the per-channel settling time when the input amplitude makes a full-scale change. The cycle time of the ADC typically consists of the conversion time and the acquisition time (tCYC = tCONV + tACQ ), which is usually specified as 1/throughput rate in the data sheet. The capacitive DAC of the SAR ADC is disconnected from the inputs at the start of the conversion, and the multiplexer channel can be switched to the next channel after a small switching delay, tS . This allows the maximum time to settle the selected channel.

To guarantee performance at maximum throughput, all of the components in the multiplexed system must settle at the ADC input between the time that the multiplexer switches and the end of the acquisition time. The multiplexer channel switching must be properly synchronized with the ADC conversion time. The achievable throughput rate of multiplexed systems is the single ADC throughput divided by the number of channels being sampled.

Figure 1

Typical timing diagram of a multiplexed data-acquisition system.

Typical timing diagram of a multiplexed data-acquisition system.

Some designers use a low-output-impedance buffer to handle the kickback from the multiplexer inputs. The input bandwidth of the SAR ADC (tens of MHz) and ADC driver (hundreds of MHz) are higher than the sampling frequency, and the desired input signal bandwidth is typically in the tens to hundreds of kHz range, so an RC anti-aliasing filter may be required at the input of the multiplexer to eliminate unwanted signals (aliases) from folding back to bandwidth of interest and to reduce settling time issues. The value of the filter capacitance used at each input channel should be carefully selected based on the following tradeoff: If the capacitance is large, it will help attenuate kickback from multiplexer, but it can also make the previous amplifier stage unstable by degrading its phase margin.

C0G or NP0 type capacitors are recommended for an RC filter that has high Q, low temperature coefficient, and stable electrical characteristics under varying voltages. The reasonable value of series resistor should be chosen to keep the amplifier stable and limit its output current. The R cannot be too large; otherwise the amplifier will not be able to recharge the capacitor after the multiplexer kickback.

36 comments on “Key Considerations for Multiplexed Data-Acquisition Systems

  1. eafpres
    August 11, 2014

    @Maithil Pachchigar–thank you for the informative article.  In a multiplexed system sharing an ADC, does this factor into the long-term reliabilty analysis of the system?  In other words, does multiplexing reduce the expected system life over a system with the same number of channels and no ADC sharing?

  2. Maithil Pachchigar
    August 11, 2014

    @eafpres1 – thank you for the comment. There are numerous applications, in which multiplexing is used and I haven't seen any case of the customer using multiplexed DAS that ran into a long-term reliability issue of the reduced system life.

  3. samicksha
    August 12, 2014

    I guess multiplexer impedance itself can degrade channels, but even after this advantages of multiplexing can help and ignore this fact.

  4. etnapowers
    August 15, 2014

    @eafpres: I think that the long term reliability of a multiplexed system depends on the quality of signals path ( i.e. insulation , quality of the metal traces , …) and it depends by the overall reliability of the components of the IC.

  5. etnapowers
    August 15, 2014

    The multiplexing is a good strategy for sure. The impedance can be driven by a proper system of multi drivers , provided that the area occupation is kept under control and the multiplexing is effective.

  6. samicksha
    August 15, 2014

    The impedance can be driven by a proper system of multi drivers , provided that the area occupation is kept under control and the multiplexing is effective.


    @etnapowers: I agree to your points about impendance can be driven by proper system, but what do you suggest as best practise here.

  7. goafrit2
    August 15, 2014

    >>  In other words, does multiplexing reduce the expected system life over a system with the same number of channels and no ADC sharing?

    I do not think there is any correlation between reliability and multiplexing systems. The weakest link will be the effectiveness of the multiplexer as in most cases, the individual channels are working alone.

  8. goafrit2
    August 15, 2014

    >> and it depends by the overall reliability of the components of the IC.

    What do you mean by components of the IC? Guess you mean the process/transistors upon which the IC is designed? Here, if the MUX is efficient, the channels wil work as designed with no apparent problem arising because they are MUX'ed.

  9. eafpres
    August 15, 2014

    @goafrit2–the question I was asking is purely based on the ADC.  In other words, ADC, like all electronics, is still a electro-physical system, subject to stress in voltage and current variations, thermal cycles, etc.  If I have an ADC with an MTBF of, say, 10,000 hours, and I use two identical ones, one w/multiplexer such that the ADC duty cycle is nearly 100%, and another one serving one set of signals of the same sort, but no multiplexing, so its duty cycle is lower, would I expect, on average, the component to fail earlier in the multiplexed system?

    I fully agree with your statement that other parts of the system are more likely to be key in overall reliability, so my question is purely theoretical.

    Thanks for your thoughts.

  10. vasanjk
    August 25, 2014

    MP

    “The R cannot be too large; otherwise the amplifier will not be able to recharge the capacitor after the multiplexer kickback.”

    This is something most designers take easy. The thinking is – “after all the multiplexer input has very high impedance, a little more in series doesn't hurt”.

     

  11. chirshadblog
    August 25, 2014

    @vasanjk: Well in an instance or two it wont but in the long run with many been accumulated, it will make things complex for sure

  12. vasanjk
    August 25, 2014

    chirsgadblog,

     

    I am curious to know how we could calculate the optimum resistor value. For different parts it could vary based on the internal characteristics of the ADC.

     

    I guess one should work backwards from the timing data of the signal range in question.

  13. Maithil Pachchigar
    August 25, 2014

    @eafpres1 — We usually declare in the datasheet that an exposure to absolute maximum rating conditions for extended periods may affect device reliability and stresses above the absolute maximum ratings may cause permanent damage to the device, therefore as long as the device is operated within the specified limits of the datasheet, its overall reliability should not be a concern.

  14. eafpres
    August 25, 2014

    Hi Maithil–thanks for your feedback.  I do have a question, though.

    It seems that becuase so many systems fail long before some of the electronics, like a mobile phone–screen gets damanged, case gets scratched up, battery fails, etc., then we get a new one.  Even for cars, most people replace them more often than their potential lifetime.

    So I wonder; we get used to some things fail, some things don't.  Yet those that don't, must fail eventually if we kept using them.  

    If we take the datasheets at face value, there is some statement of reliability, maybe MTBF, or # of cycles, etc.  So there is an expectation that if we took a population of these parts, as we got closer to or past the spec value, we would expect to see the frequency of failures increase.

    So what happens to equipment that is intended to be used for decades?  Will super high performance high-density sub 20 micron parts become the achilles heel?

  15. Maithil Pachchigar
    August 26, 2014

    eafpres1 – Analog Devices offers the reliability data for a particular product depending on the wafer fabrication/process and assembly/packaging technology. Go to ADI Home page > click  Quality & Reliability > click Reliability Data

  16. eafpres
    August 27, 2014

    Hi Matihil–thank you for the direction to the reliability data.

    As I understand the use of such data, suggesting a MTBF or other reliability figure from a test with 0 failures requires assumption of the failure distribution, and of course is associated with a particular set of operating conditions.

    I did look at some of the packaged process specs; one I selected had many many items showng passing HAST with 0 failures.

    To me, I wonder then what would cause a part to fail?  In my past experience, HALT/HAST was intended to find failure modes, not failure rates.

    Anyway, thanks for the data.  For me, I will still expect my electronics to fail, even if is after I am long gone.

  17. goafrit2
    September 2, 2014

    >> The thinking is – “after all the multiplexer input has very high impedance, a little more in series doesn't hurt”.

    Actually, I did not get the point in this quote. Technically, you should not be in series to start with to have a MUX.

  18. goafrit2
    September 2, 2014

    >> I guess one should work backwards from the timing data of the signal range in question.

    That is not always the best way of doing this. It can take months to get a product done. Any circuit can be analysed irrespective of the degree of difficulty. What is really needed is spending time to design before implementing. These days we then to design with the help simulators which may not be optimal.

  19. goafrit2
    September 2, 2014

    >>  therefore as long as the device is operated within the specified limits of the datasheet, its overall reliability should not be a concern.

    Nevertheless, that does not mean components cannot degrade with age. If you have MEMS gyro made today and opeate it within all stated conditions, it does not mean it will perform optimally in a car in 15 years where even the silicon itself is aging. That is a big issue – can someone claim reliability is guaranteed in a 15 year old car!

  20. Maithil Pachchigar
    September 3, 2014

    Agree. Therefore,  Analog Devices offers the quality and reliability data for a particular product depending on the wafer fabrication/process and assembly/packaging technology. Go to ADI Home page > click  Quality & Reliability > click Reliability Data

  21. etnapowers
    September 12, 2014

    @samicksha: it depends on the costs of the multi drivers solution compared to the budget available for this project. An early evaluation of costs and benefits can help the designer to choose the best solution in terms of profitability.

  22. etnapowers
    September 12, 2014

    @goafrit2: I mean the single blocks that constitute the ADC. The reliability of the MUX is a key point , provided that there are no issues on the channels that have to be multiplexed.

  23. goafrit2
    October 7, 2014

     Go to ADI Home page > click  Quality & Reliability > click Reliability Data

    Thank you – I have used most of the Applications Notes which have lots of great value to me

  24. goafrit2
    October 7, 2014

    If you assume that transistors/silicon is free especially when integrated, there is nothing to worry. You can easily and efficiently add that small units within the product. The key is that more integration helps your product perform better with minimal loses in efficient.

  25. goafrit2
    October 7, 2014

    he reliability of the MUX is a key point , provided that there are no issues on the channels that have to be multiplexed.

    Every aspect is an issue but from my experience, analog MUX can be easily designed. In most chips, you can add MUX to test chips and that happens without major issues. One of the major problems to note is your process maturity which can affect lots and how the product performs.

  26. etnapowers
    October 14, 2014

    “The key is that more integration helps your product perform better with minimal loses in efficient.”

     

    @goafrit2: I agree on this point. I add that more components integrated implies an increased risk of a failure of one of the added components.

    Henry Ford said: “The only part of a car that cannot be broken is the one that is not present inside the vehicle”

     

  27. etnapowers
    October 14, 2014

    “One of the major problems to note is your process maturity which can affect lots and how the product performs.”

     

    @goafrit2: I agree on what you said about MUX circuitry that usually does not have problems, there is a well known set of design rules for it. The technology is the key factor , a well established technology guarantees robustness and effectiveness, because all the possible issues are known by mean of reliability and qualification trials, conducted on test vehicle ICs built in that technology.

  28. goafrit2
    November 3, 2014

    >>  I agree on this point. I add that more components integrated implies an increased risk of a failure of one of the added components.

    That is the key point. The risk of failure of system is largely the same as of a sub-system in circuit design as area cost has become negligible. If you can pack all together, do so as that saves you many worries.

  29. goafrit2
    November 3, 2014

    >> The technology is the key factor , a well established technology guarantees robustness and effectiveness, because all the possible issues are known by mean of reliability and qualification trials

    The problem with process maturity is that as soon as it is matured and established, management pushes for a new process and the whole circle begins from afresh.

  30. etnapowers
    November 10, 2014

    @goafrit2: your post underlines the importance of the block design and of IP reuse, that is a common practise of the companies producing ICs, especially the big companies, that have a wealth of resources and know how to assemble well-working system on package.

  31. etnapowers
    November 10, 2014

    @goafrit2: this is a common issue that sometimes can be anticipated by some feasability studies and qualification trials, to make the transition to the new technology more effective. I realize that this is not always possible.  

  32. etnapowers
    November 10, 2014

    “The problem with process maturity is that as soon as it is matured and established, management pushes for a new process and the whole circle begins from afresh.”

     

    This conflict is often due to the need of new features. It is what the market demands, and  the management  pushes for having  new products that satisfy the new requirements of the market, but the managers don't know if it is technically feasible and they ignore what problems may arise during the phase of transition from a consolidated technology to a new one. 

  33. fasmicro
    November 10, 2014

    >> your post underlines the importance of the block design and of IP reuse,

    No matter the size of any company, mastering the art of IP reuse will save lots of money on product development. It should not be for only big companies.

  34. fasmicro
    November 10, 2014

    >> this is a common issue that sometimes can be anticipated by some feasability studies and qualification trials, to make the transition to the new technology more effective. 

    There is an inherent cost associated with adoption of new things including technology. The cost of not doing so is obsolescence. If you are afraid of moving to new process because of learning new process issues, you cannot compete.

  35. etnapowers
    November 17, 2014

    @fasmicro: I agree with you on this should be the approach for all the companies. However in real world only big companies have the funds to build a big portfolio of IPs, although it should be a recommendable policy for all the companies.

  36. etnapowers
    November 17, 2014

    @fasmicro: I couldn't agree more with you! Innovation is the key process to compete, otherwise a company is destined to survive for a while and then to cut its development plans.

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