Multiplexing allows the use of fewer ADCs per system, offering significant savings in power, size, and cost. Successive-approximation ADCs — often called SAR ADCs for their successive-approximation register — have low latency, making them popular in multiplexed systems that demand fast response to a full-scale input step (worst case) without any settling time issue. Easy to use, SAR ADCs offer low power and small size.
This article focuses on the key design considerations, performance results and application challenges associated with multiplexed data-acquisition systems using high-performance precision SAR ADCs.
When the multiplexer input channel is switched, the ADC driver amplifier must settle a large voltage step within the specified sample period. The input can change from negative full-scale to positive full-scale, or vice versa, so a large input voltage step can be created in a small time. The amplifier must have a wide signal bandwidth and fast settling time to handle this step. In addition, nonlinear effects appear as a result of slew rate or output current limitations.
Also, the driver amplifier must settle the kickback caused by charge rebalancing on the SAR ADC input at the start of the acquisition period. This could become the bottleneck in settling the inputs in multiplexed system. Settling time issues can be reduced by lowering the throughput rate of the ADC, which provides longer acquisition time and allows the amplifier sufficient time to settle to the required accuracy.
The timing diagram in Figure 1 shows how to optimize the per-channel settling time when the input amplitude makes a full-scale change. The cycle time of the ADC typically consists of the conversion time and the acquisition time (tCYC = tCONV + tACQ ), which is usually specified as 1/throughput rate in the data sheet. The capacitive DAC of the SAR ADC is disconnected from the inputs at the start of the conversion, and the multiplexer channel can be switched to the next channel after a small switching delay, tS . This allows the maximum time to settle the selected channel.
To guarantee performance at maximum throughput, all of the components in the multiplexed system must settle at the ADC input between the time that the multiplexer switches and the end of the acquisition time. The multiplexer channel switching must be properly synchronized with the ADC conversion time. The achievable throughput rate of multiplexed systems is the single ADC throughput divided by the number of channels being sampled.
Some designers use a low-output-impedance buffer to handle the kickback from the multiplexer inputs. The input bandwidth of the SAR ADC (tens of MHz) and ADC driver (hundreds of MHz) are higher than the sampling frequency, and the desired input signal bandwidth is typically in the tens to hundreds of kHz range, so an RC anti-aliasing filter may be required at the input of the multiplexer to eliminate unwanted signals (aliases) from folding back to bandwidth of interest and to reduce settling time issues. The value of the filter capacitance used at each input channel should be carefully selected based on the following tradeoff: If the capacitance is large, it will help attenuate kickback from multiplexer, but it can also make the previous amplifier stage unstable by degrading its phase margin.
C0G or NP0 type capacitors are recommended for an RC filter that has high Q, low temperature coefficient, and stable electrical characteristics under varying voltages. The reasonable value of series resistor should be chosen to keep the amplifier stable and limit its output current. The R cannot be too large; otherwise the amplifier will not be able to recharge the capacitor after the multiplexer kickback.