Editor’s note: Recently, Tamara Schmitz and Mike Wong of Intersil Corp authored a three-part series in Planet Analog on the basics of bypass capacitors, entitled “Choosing and Using Bypass Capacitors.” The positive response was overwhelming, and a few respondents even asked for more. The most helpful critique came from a competitor, and in the spirit of intra-industry education, they are teaming up to offer Part 4.
You can read the previous parts by clicking on the corresponding link:
Part 1 : www.planetanalog.com/showArticle.jhtml?articleID=199905522
Part 2 : www.planetanalog.com/showArticle.jhtml?articleID=199905942
Part 3 : www.planetanalog.com/showArticle.jhtml?articleID=200001206
Knowledge of the fundamentals of bypass capacitors prepares you to protect and improve the power supply. Recall the basics: a bypass capacitor is employed to conduct alternating current around a component or group of components. Also known as filter capacitors (caps), bypass capacitors are found in every piece of electronic equipment because there are always systems, circuits, and individual ICs that need to be bypassed, to ensure that ac noise is dampened.
In every situation or application, there is no substitute for accurate modelling and simulation. When taking into account all of the parasitics of the packages and printed circuit board, a true picture can be made of the frequency response of the power supply. Some surprising interactions appear when modelling a real bypass network. The goal of this installation is to reveal these interactions and empower the designer to minimize them appropriately for the desired application. A summary of common practices is provided in the conclusion.
The key to a useful simulation is effective modelling. In modelling a bypass network, the capacitors have parasitic resistance and inductance associated with the package and board connections. Manufacturers vary in their ability to supply good models. Sometimes capacitor datasheets are generic, covering an entire family of components, so the parasitic values they contain are not specific or even unrealistic; apply a sanity check. Table 4 of Part 2 of this series is good working information.
When you need to have more accurate information than this, carefully check what you download or what your representative sends you. RF components usually have good and accurate models, but the same is usually not true of everyday electronic components, sadly.
The goal of bypassing is to provide a low-impedance connection to ground over the frequencies of interest. A single capacitor has the expected low-pass performance, but also a high-pass response due to the parasitic series inductance. This creates a notch behavior in the frequency spectrum. The depth of the notch is related to the “Q” or quality factor of the component.
A series resistance reduces the Q of the circuit, and can be added to soften the slope in the valley region near the resonant frequency, as we’ll show in a moment. The trade-off to using a series resistance with a single capacitor is that the minimum impedance value is sacrificed. Sometimes a series resistance is inevitable, coming from trace resistance on the printed circuit board.
There are lots of situations where one capacitor does not provide enough bypassing, so multiple capacitors must be used. Cost and area usually limit the number of capacitors used for bypassing. To optimize the values and sizes of capacitances included, there is no substitute for simulation.
Frequently, in the lab and under time pressure, capacitors are copiously added until the needed circuit performance appears. Which capacitors should you add and why? Identical values of capacitance placed in parallel will just lower the impedance value uniformly versus frequency. Different values of capacitance will broaden the bandwidth where low impedance appears, provided that you attend to the issues we’re about to cover. Otherwise, it could be a case of more definitely being less! Let’s look at some cases:
Case 1: FPGA Bypassing
Figure 1 is a simulation of the configuration which was previously sketched out in Figure 10 of Part 2 of these articles. It’s a common combination of capacitors used by engineers to provide decoupling at the wide range of frequencies that a modern digital circuit could throw back into a system through its supply pins. We’ve used the common “10x rule” introduced in the previous parts as a starting point for value selection.
Figure 1: Three capacitors decoupling the supply to an FPGA
(Click on image to enlarge)
(A note on the vertical scaling, to be explicit: the log of impedance is plotted, with 0 dB corresponding to 1 O, -20 dB to 0.1 O and so on. See the color-coded mini-schematic key in each figure, which shows which trace goes with which capacitor.)
In this simulation and in the others to follow, we’ve taken a default value of 10 mO (0.01 O) for the effective series resistance of the capacitor. This allows for some resistance of the PCB traces, vias, and joints, as well as typical values of internal resistance. We’ll see later that the value of this resistance is important and that lower is not always better.
Immediately obvious from considering the black (composite) trace is that the impedance of the parallel network of the three capacitors is higher than any of the individual capacitors in two distinct regions. How can this be? The full circuit theory proof, showing that between any two impedance nulls (zeroes) you must get an impedance peak (a pole), goes beyond our scope here (Reference ). To gain some intuition, think of the admittance of each of the individual capacitors in parallel.
Let’s first discuss single, ideal components. A perfect capacitor has an admittance which has no real part and a positive imaginary part proportional to frequency. A perfect inductor also has an admittance with no real part, but a negative imaginary part which falls with frequency. A series LC circuit looks like a capacitor at low frequencies and like an inductor at high frequencies. Therefore, we know that the sign of the imaginary part of its admittance must flip at some frequency, and indeed it does, at the resonant frequency of the L and the C value.
So when we put several of these bypass capacitors (each with different L and C values) in parallel, the negative and positive pieces of imaginary part of the admittance will cancel at certain frequencies. Zero admittance equals infinite impedance, hence the vertical peaks in Figure 1. The actual value of the peak is limited by the residual resistance of the bypass capacitor which are real and positive. If we play around with these resistances, we can see that we’ll not only change the depth of the impedance notches, but also the height of the peaks. That’s useful, so hold that thought!
While we have a few peaks, it’s probably nothing to lose sleep over (well, in a video system, those peaks would be near frequencies related to the pixel clock, so don’t ignore it completely). Allowing a little series resistance to creep into one of the capacitors, perhaps by choosing a chemical capacitor for the 1 µF part, will provide some control, as we’ll see in the next case. The motivation for using a large number of capacitors in parallel is that the impedance nulls can be spaced relatively closely, and for the same quality of capacitor, this stops the peaks from getting too high. This likely explains the popularity of this methodology; it certainly makes the capacitor manufacturers happy.
Note also that the high frequency impedance of the composite network is significantly lower than that of any of the individual capacitors; this would be the case whether or not we had spread the capacitor size range out. The explanation is simple: putting inductors in parallel lowers their impedance too!
Case 2: Op-amp Bypassing
Here’s another popular parallel combination, recommended by applications engineers the world over. We’ve put a 4.7 µF 1206 capacitor (for some low-frequency control) on the supply rails of an op-amp and a 0.1 µF 0603 cap (to keep the thing happy at high frequencies).
The impedance is plotted in Figure 2 .
Figure 2: Two capacitors in parallel, decoupling an op-amp supply
(Click on image to enlarge)
Fortunately it’s easy to get rid of that 11-MHz peak. Increasing the series resistance associated with the 4.7uF from 0.01 O to 0.1 O (this is still a low value) significantly changes the impedance curves, Figure 3 .
Figure 3: Increasing the series resistance of the 4.7 µF capacitor to 100 mO
(Click on image to enlarge)
The moral of this story is that when you replace tantalum supply-decoupling capacitors (with higher series resistance) for ceramics (with lower series resistance), your system might suffer a catastrophe. Just because new components are now available in the right case sizes, your reliability people say they are better, your materials people say the ceramics are cheaper and every other department is using them, doesn’t mean they are the best choice.
Case 3: RF and Baseband Bypassing
In the op-amp case our frequencies of concern are quite low, rarely exceeding 100 MHz. For the FPGA, we want to control high-frequency emissions and make sure glitches don’t impact our logic noise margins. But in this example, we really do need to pay special attention to high frequency phenomena, since the power supply serves a low-power radio transceiver operating around 800 MHz.
There is also a digital baseband circuit with a lot of activity at the system clock rate of 16 MHz. We could use a wideband network with an array of capacitor values, but space is an issue. By the way, the board designer only laid out for two supply decoupling components on the board; one 0402 and one 0201 (it’s a very small system).
So we’ve chosen a 220 nF 0402 capacitor, the highest value we can currently get in that size, and a 100 pF (yes, picofarad) 0201 capacitor. The individual resonant frequencies of these components work out well for the two critical frequencies of concern. The frequency response of the bypass network is plotted in Figure 4 .
Figure 4: Trying to decouple a sensitive RF circuit over a wide range of frequencies
(Click on image to enlarge)
As RF designers know, resonant circuits are just about the only way to make high impedances at these frequencies. You can be pretty sure that this radio’s performance is going to be impacted in some way by the fact that the supply pin looks like an open circuit at about 560 MHz. In this particular system, that’s the frequency of one of the local oscillators, so this is about the worst combination possible!
Once again, the trick of putting some resistance in series with one of the capacitors can come to our rescue. Figure 5 shows the effect of sweeping the series resistance of the 220 nF capacitor from 10 mO up to 1 O in half-decade steps.
Figure 5: Increasing the series resistance reduces the impedance peak!
(Click on image to enlarge)
This is a clear case where series resistance is needed to provide an optimized bypass network. Without simulation, the impedance peaks may have crippled our bypass network, making the circuit susceptible to noise at those frequencies.
Bypassing is often assumed to be simple: “just toss a few caps on the power-supply pins.” Many times that is sufficient. However, as cost, size and portability force engineers to optimize every component, bypass networks deserve simulation time and critical analysis akin to the other blocks in the system.
Here’s a summary of bypass considerations raised by this article:
1. Bypass close to IC pin and ground (minimize Rseries for deep notches, optimize it for smoother overall impedance)
2. Use multiple values in broadband applications (or in the presence of broadband noise), spacing the resonant frequencies out over the band you need to cover
3. More capacitors won’t hurt the power supply! They just add area, cost and design time.
4. To be sure, simulate (any simulator will do, even a free one). Quantify parasitics and model correctly, applying common sense to the component parasitic values
5. Loss can be good! Higher-performance capacitors may not be best in your circuit.
6. Resonance (impedance nulls) can be useful, be sure to predict and employ
7. Anti-resonance (impedance peaks) can get you into trouble, so predict and avoid!
Gabor C. Temes and Jack W. Lapatra, “Introduction to Circuit Synthesis and Design (Networks & Systems), ” McGraw Hill, ISBN 0-07-063489-0
About the authors
Kendall Castor-Perry of Gennum Corp. has been practicing the electronic arts for over three decades, having designed a multitude of industrial instrumentation, communications systems and audio circuits. More recently he’s spent a lot of time supporting both customers and colleagues, helping them to chase signals back and forth through various scary analog, digital and modulation domains.
Tamara (Papalias) Schmitz is a principal application engineer for analog applications at Intersil Corp. She is also a full-time professor of Electrical Engineering at San Jose State University. She has a BSEE, MSEE and PhD in RF CMOS design from Stanford University.