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Latchup and its prevention in CMOS

Early CMOS processes suffered a reliability concern that became known as latchup. It resulted in circuits either malfunctioning or consuming excessive power, and could be either inherent in the design or triggered by voltage spikes on IO pads that could forward bias PN junctions they were connected to.

To understand why latchup can occur, consider the simple inverter in Figure 1.

Figure 1

A typical CMOS inverter cross section, showing parasitic devices.

A typical CMOS inverter cross section, showing parasitic devices.

The inverter consists of two MOS transistors. Also placed somewhere nearby (not necessarily between the devices as in the diagram) are well and substrate taps to bias the well to VDD and the substrate to VSS. There are also parasitic bipolars: a vertical PNP device formed by the P+/N well/P Substrate junctions, and a horizontal NPN device formed by the lateral N+ / P substrate / N well junctions.

A simplified schematic of the parasitic elements is shown in Figure 2. The shunting resistors Rwell and Rsub represent the effective resistance from the well tap to the PNP base and the substrate tap to the NPN base.

For the circuit to latch up, several conditions must be met1 .

  1. The transistor current gain product of Qn and Qp must be greater than 1 such that the structure will remain latched.
  2. Both emitter-base junctions of Qn and Qp must be forward biased to initiate and sustain latchup.
  3. The power supply must be able to sustain the supply current drawn while latched (the holding current ) and the supply voltage (the holding voltage ).
Figure 2

Simplified schematic of the parasitic devices in the above CMOS inverter layout.

Simplified schematic of the parasitic devices in the above CMOS inverter layout.

The holding current has been shown2 to be strongly dependent on Rwell and Rsub. The physical reason is clear: a low Rwell or Rsub means a higher current has to flow to maintain forward bias on the base-emitter junctions. Note that Figure 1 represents a ‘strong’ layout as the substrate and well taps are between the devices; if they were e.g. on the other sides of the devices then Rwell and Rsub would increase and the circuit would become more sensitive.

There are several ways to reduce the possibility of latchup:

  1. Reduce the beta of either or both parasitic devices. In practice this can be achieved by increasing the spacing between the devices, which increases the width of the lateral device. However, such increased spacing reduces packing density.
  2. Increase well and substrate doping concentrations to reduce Rwell and Rsub. For example using retrograde doped wells.
  3. Provide alternative (or better) collectors of the minority carriers. For example the use of guard rings around devices.

In practice a combination of process techniques and layout techniques such as appropriate provision of well/substrate taps and/or guard rings can be used.

Figure 3

Guard ring implementation implemented by an automated layout generation tool.

Guard ring implementation implemented by an automated layout generation tool.

Figure 3 shows a typical guard ring implementation around a common centroid device. Automated generation of guard rings using constraints allows them to be generated quickly and reliably. Guard rings are also widely used to reduce substrate noise coupling, a topic for the next blog posting.

1 Gregory, B.L. & Shafer, B.D. “Latchup in CMOS Integrated Circuits”, IEEE Trans Nuc. Sci. v NS-20 p293 Dec 1973.

2 Rung, R.D. & Momose, H. “DC holding and dynamic triggering characteristics of bulk CMOS latchup”, IEEE Trans. Electron Devs. V ED-30 p 1647 Dev 1983.

5 comments on “Latchup and its prevention in CMOS

  1. amrutah
    January 20, 2015

    Keith: Thanks for this blog post.

       If we start operating at lower supply voltages, the reliability of the device can be improved due to latchup.  Do you see any problems with this?

  2. Keith Sabine
    January 22, 2015

    Amrutah,

    Good question. Lower supply voltages help because the turn on voltage for the lateral parasitics is pretty independent of scaling – but there are many variables involved, like the distance of the base region of the parasitics (which decreases, hence potentially higher gain) and the resistance of the well/substrate etc. I'd be interested in hearing from others with practical experience of latchup resistance vs. scaling.

    regards

     

    Keith

  3. amrutah
    January 22, 2015

    Keith,

      I see another issue with the parasitic BJT.  Now when we have strong subtrate contacts/ guardrings around the devices, we form a lateral NPN (N+ of NMOS, P-sub guard ring, N-well guard ring).  Most of the times with P-sub connected to ground, will this cause any problem?

  4. amrutah
    January 22, 2015

    Keith,

       Thanks, I had never explored the effect of voltage scaling on the Latchup.  It will be interesting to understand more on this topic.

  5. Keith Sabine
    February 19, 2015

    Hi Amrutah,

    The strong well/substrate guard ring connections should help with latchup prevention as they reduce the well/substrate resistances and will help prevent forward biassing of the parasitic BJTs. So  no, I don't see a problem.

    Also guard rings are widely used to reduce substrate noise (this is a topic for another blog!) and so are generally a good thing.

    regards

    Keith

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