Lattice unveils development platform for SERDES and video clocks

Lattice Semiconductor Corporation has unveiled of an evaluation board for the ispClock 5400D programmable clock device.

The new board is an easy-to-use platform for evaluating and designing with the ispClock5400D differential clock distribution device. The evaluation board can be used by itself to review the performance and in-system programmability of the 5400D device, or as a companion board and clock source for LatticeECP3 FPGA Serial Protocol or Video Protocol evaluation boards.

Typically, expensive oscillators with LVDS or LVPECL interfaces are used as a reference clock for FPGA SERDES interface applications. The ispClock5400D device provides ultra low-jitter differential clock outputs that can be used to drive both the general purpose clocks and the SERDES reference clocks for FPGAs, ASSPs and ASICs. The evaluation board demonstrates how to interface a low-cost CMOS interface oscillator to the ispClock5400D device to produce high quality clocks for XAUI applications or 270 MHz SDI video applications.

“This new evaluation board provides an excellent development platform for differential clock implementations with the ispClock5400D device. The platform provides a way to interface rapidly to bench test equipment to confirm the low period and phase jitter performance of the 5400D family,” said Shyam Chandra, Lattice's Product Manager for Mixed Signal Devices. “Traditional clock distribution ICs do not help with timing challenges in a circuit board; in fact, in many cases fixing timing problems requires new circuit board layout and fabrication. Our new evaluation board showcases the skew control flexibility of the ispClock5400D device, which costs far less than traditional clock distribution ICs.”

The ispClock5400D evaluation board is a versatile, ready to use hardware development platform for evaluating and designing with ispClock programmable clock devices. The platform is based on a 6 x 4inch evaluation board that features the ispClock 5406D device in a lead-free 48-pin QFNS package, SMA connectors and crystal oscillator circuits, as well as expansion headers for JTAG, I2C bus and test. The kit includes a preconfigured ispClock5400D demonstration design that illustrates the low-jitter performance and time/phase skew output control of the device. The board is controlled with switches and push buttons. A pin header provides access to the I2C bus interface of the ispClock5406D device.

Users may extend or modify the preconfigured demo using PAC-Designer and ispVM software.

Availability and Pricing

Pricing for the ispClock5400D evaluation board is $169. The boards are available for immediate ordering. All ispClock5400D and LatticeECP3 devices are fully production qualified and available now for volume shipments.

Related link:

ispClock5400D evaluation board

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