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Layout-Dependent Effects in Analog Design

Analog designers have always had to worry about physical layout to get good matching of devices. Variations in doping levels across the chip, usually assumed to be in a gradient in one or two dimensions, could be handled by clever layout such as common centroid devices. The same is true for temperature variations created by on-chip power devices: With currents of 10 A or more on power conversion/regulation devices, thermal gradients become a real issue.

As process geometries reduced, a new type of variability was introduced — collectively known as “layout-dependent effects,” LDE for short.

One example of an LDE is the proximity of devices to the well edges. The distance of devices to a well edge has an effect on the Vt (threshold voltage) of the device. The cause is implant ions scattering off the resist sidewall used to define the well, thus increasing Vt by several, or even tens, of millivolts. (See “Layout-Dependent Proximity Effects in Deep Nanoscale CMOS,” John V Faricelli, IEEE CICC 2010.)

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The change in Vt can give rise, not only to mismatch effects, but also to significant performance changes. Other effects can be due to unintentional stresses in the silicon, caused, for example, by shallow trench isolation between devices. This stress affects carrier mobility in the devices and, hence, current. This is known as “length of diffusion” or LOD effect, where the characteristics of a device vary according to the distance of its gate from the diffusion edge.

To design with LDE effects, various layout techniques can be used:

  • Use similar diffusion size, shape, orientation
  • Use a larger separation for devices to the well edge
  • Add dummy devices and/or dummy poly to make fingered devices more equal

However, accurate simulation of the design requires early layout and, with it, parasitic extraction, to be able to model the LDE effects during simulation. All this breaks existing custom design flows, which traditionally have a circuit designer hand off a preliminary schematic, simulated possibly with estimated parasitics, to the layout engineer, who then creates an initial layout for extraction of real parasitic. This then gets handed back to the circuit design to optimize device parameters to meet the performance goals, and often takes several layout/optimization iterations.

An automated analog layout tool, such as Pulsic’s Animate, can identify constraints intended by the designer and rapidly generate multiple real layouts in minutes. These layouts can then be extracted and simulated, allowing designers to take into account LDE effects much more quickly without sacrificing performance.

8 comments on “Layout-Dependent Effects in Analog Design

  1. goafrit2
    October 11, 2014

    >> An automated analog layout tool, such as Pulsic's Animate, can identify constraints intended by the designer and rapidly generate multiple real layouts in minutes. 

    Analog layout is a big element in analog design. While a mixture of autorouting and manual works, I think the best model remains to manually rout all the critical signals. Layout is a big design phase that must be invested. Auto-routing works but not for all signals.

  2. fasmicro
    October 11, 2014

     However, accurate simulation of the design requires early layout and, with it, parasitic extraction, to be able to model the LDE effects during simulation.

    Always do good LVS with accurate models of the parasitics. This is the most important aspect of this business. If your models are not good, you have no chance of success. Layout Vs Schematic (LVS) will help fix any issue that can make the layout not to match the schematic. Your CAD must have a good one for you to have a great product

  3. bjcoppa
    October 12, 2014

    More companies have become chip design firms over fab based providers to reduce capital costs. TSMC has become the leading chip provider in the world as more companies outsource production overseas. It also makes TSMC's job easier as it can consolidate designs for a larger common customber base but it stunts creativity and innovation in the industry.

  4. Keith Sabine
    October 17, 2014

    While traditionally people did route critical nets first, and sometimes finish the routing of non-critical nets automatically, the problem with this approach is that you need a good placement as a starting point. 'Good' means you can complete the routing without shorts or opens. Because placement didn't consider routing, or merely made some estimate of it, designers often ended up doing things manually, This can take hours – even for just an opamp.

    Animate solves placement and routing as a single problem, so no experimenting with different placements until you get a routable result. And you can set constraints on critical nets such that e.g. the width, spacing, shielding etc. are honoured. The same opamp can be placed and routed in seconds, and you don't get just one result but many, so you can pick the one you like, and get parasitics for simulation much earlier than by any manual method. You can then tweak the layout either by altering the constraints or by manual editing.

    Of course some types of layout will probably never be automated, like RF for example. But for many applications such as IP generation where time is critical, automated layout offers real benefits over traditional manual layout.

  5. fasmicro
    November 3, 2014

    >> More companies have become chip design firms over fab based providers to reduce capital costs.

    That is the core of TSMC's strategy. No many companies can wake up and invest billions of dollars to match its capacity. The singular reason that TSMC is not a product company also works for it as it does not pose a threat as Samsung does when it makes product parts for Apple.

  6. fasmicro
    November 3, 2014

    >> While traditionally people did route critical nets first, and sometimes finish the routing of non-critical nets automatically, the problem with this approach is that you need a good placement as a starting point.

    The reverse is a better strategy – Start by routing critical nets manually and then autoroute the non-critical ones. I have used Protel and you can set such that it cannot change already routed nets. In digital VLSI, you can also do same with many of the tools in the market. Route critical nets manually and finish with autorouting.

  7. uchiha
    November 4, 2014

    @fasmicro: Well it's a precautionary step isn't it ? Do you think by doing this we can mitigate the risk ?

  8. fasmicro
    November 8, 2014

    >> @fasmicro: Well it's a precautionary step isn't it ? Do you think by doing this we can mitigate the risk ?

    Yes, you can mitigate the risk. The problem in layout is to think that “marketing features” like autorouting can give a decent work. Those features are there so that you do not complain and ask about them when the marketer comes to sell things.

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