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Layout guidelines help manage video equalizer’s return loss (Part 3 of 3)

(You can read Part 1 here and Part 2 here.)
Case Study: Optimizing the equalizer evaluation board for return loss

A brief examination of the exercise performed to optimize the design of the Cypress Video Equalizer evaluation board (Figure 11 ) demonstrates how the different layout guidelines discussed previously can be used to optimize return loss.



Figure 11: Evaluation board used to assess performance
(Click on image to enlarge)

The board was designed as shown, with minor differences. The board shown here is the one that gave superior return-loss performance and is currently being used. Table 1 shows the six board variants that were used for this exercise.



(Click on image to enlarge)

Version 3.0a identifies the base version of the 3.0 revision of boards. Compared to the previous revision, removing the thermal reliefs of the BNC connector's soldering pads and adding direct vias to ground improved return loss. This is common to all variants in this revision.

The 'Trace Width' field denotes the width of the traces from the BNC connector to the return-loss network and then on to the SDI inputs of the equalizer. The 14-mil value is the calculated width for a characteristic impedance of 75 Ω, using a 2D field solver. The 'TearDrop' and '40 mil' trace widths in revisions 3.0d and 3.0e, respectively, are an attempt to smooth the transition from a trace to the soldering pads of the components.

The 'AirGap' field refers to the distance between the BNC connector's center pad and the closest metal plane. 37 mil is the calculated value from the 2D field solver for a characteristic impedance of 75 Ω. 145 mils is the interpreted gap from the datasheet of the BNC connector (Trompeter UCBBJE20).

Versions 3.0a, 3.0b and 3.0b+ have the BNC via thermal reliefs present to connect the pad to ground. Except for the base version 3.0a, power and ground plane 'cutouts' are present in all the versions.

Test Procedure
For each board revision, two boards were built and each populated with a Cypress Video Equalizer. The return loss measurements were taken using the network analyzer using the procedure detailed earlier in this note. Tests were performed at room temperature with a supply voltage of 3.3 V.

Table 2 shows the results of the return loss measurements, and Version 3.0d is the clear winner.



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Figure 12 is a screenshot of the return-loss profile across frequency, taken from the network analyzer of Vision 3.0d board.



Figure 12: Return-loss profile of board Version 3.0d

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The profile shows that the return loss at 1.485 GHz is approximately 27 dB, and at 3.0 GHz is approximately 10 dB. Between these two frequencies, the return loss is always lower than that at 3.0 GHz. This meets SMPTE's return loss specifications at the relevant data rates.

In addition to this, tests with different inductor values in the return loss matching network show that an inductor value of 5. 6 nH results in the best return loss performance of approximately 30 dB at 1.485 GHz.

Conclusion
As a concluding note, the purpose of the above discussion on return loss is to demonstrate its importance to design of high-speed signaling systems. Previously, RF systems were the only ones that fit this category, but current video-transmission rates have increased enough to make return loss a critical design specification for the video broadcasting systems. Hence, it is important for everyone from semiconductor manufacturers, to board and system designers, to understand the implications of their choices of board layout design, components, materials and circuit topology.

References
1. “Using S-parameter data effectively,” Wilfredo Rivas-Torres, Agilent Technologies, Planet Analog , March 27, 2006.
2. “The Smith chart: more vital after all these years,” Bill Schweber, EDN , March 18, 1999.
3. “Return Loss Layout Guidelines for the Video Cable Equalizer,” available at www.cypress.com.

About the Authors
Mukund Krishna is an Applications Engineer for the lighting solutions group (EZ-Color) at Cypress Semiconductor Corp.at San Jose, CA. His responsibilities involve development and evaluation of demo systems, supporting customer designs from initial concept to design completion, creating product collateral and new product definitions. His experience at Cypress involves being an applications engineer for physical layer devices for high-speed communication interfaces including professional video broadcast. Mukund received an MSEE from the University of Southern California. He can be reached at ukk@cypress.com.

Jeff Hushley is a Staff Applications Engineer at Cypress Semiconductor Corp. His expertise is in the characterization and systems analysis of high-speed serial digital communication devices in broadcast and consumer video applications. He has a Bachelors Degree in Computer Engineering from the University of Toronto. He can be reached at fre@cypress.com.

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