Pole-zero compensators are used to modify the magnitude and phase of feedback amplifier loops. This article goes beyond the textbook level of explanation to consider some of the less obvious design aspects of their use, and even their design using transistors.

Pole-zero compensators can be either *lead-lag* or *lag-lead* compensators. They are often found in circuits and control theory textbooks. The most common passive-circuit compensators have three components, two resistors and a capacitor. The circuit shown below is placed somewhere that is convenient in an amplifier, especially in a feedback loop, to provide additional phase or high-frequency magnitude â€śemphasisâ€ť.

The circuit is essentially an RC differentiator with the addition of *R _{1} * shunting

*C*. The

*R*,

_{1}*C*combination has an impedance of

Then the transfer function is the voltage-divider formula,

The first factor is the *quasistatic* (0+ Hz) gain, which is the voltage divider without *C* . The dynamic or frequency-dependent factor has one zero at * Ď‰ _{z} * = â€“1/

*R*x

_{1}*C*and a pole at

*Ď‰*= â€“1/(

_{p}*R*||

_{1}*R*) x

_{2}*C*. When using Bode or

*frequency-response*graphs, the magnitude of the frequency,

*Ď‰*, which is its absolute value, is used and the negative signs are dropped. However, keep in mind that the pole and zero frequencies on Bode plots are

*not*of positive poles and zeros – not usually, anyway, and if they are, they are still plotted as positive.

Because the paralleled resistors have a lower resistance than *R _{1} * , they also have a lower time constant and thus a higher frequency; the pole frequency is at a higher frequency than the zero. As frequency increases from a low value, the zero begins to contribute positive (leading) phase at about a decade below

*Ď‰*, increasing linearly at 45

_{z}^{o}/dec until at

*Ď‰*it is +45

_{z}^{o}. Then a decade higher, it reaches a full +90

^{o}; its phase influence reaches a decade on each side of

*Ď‰*. Similarly, the pole has an equal phase range of Â± one decade around

_{z}*Ď‰*but linearly contributes â€“45

_{p}^{o}/dec of negative (lagging) phase on each side of

*Ď‰*instead. At

_{p}*Ď‰*, the phase contribution of the pole is â€“45

_{p}^{o}. (The maximum error of the linear approximation of phase for a pole or zero is about +/-6

^{o}.)

If * Ď‰ _{p} * >

*Ď‰*by more than two decades, then there is no phase interaction between pole and zero, and the full +90

_{z}^{o}of phase from the zero can be realized. The phase lead of the zero is placed near where the loop gain magnitude, ||

*GH*|| = 1, at the

*transverse*or

*unity-gain*or

*crossover*frequency of the loop,

*f*. For ||

_{T}*GH*|| < 1, the loop does not have enough feedback magnitude (which is the same as sine-wave amplitude) to sustain oscillation. The usual problem in feedback circuits is that there is too much phase lag or delay, and the phase shift around the loop - the phase of the loop gain,

*GH*– is too close to â€“180

^{o}(â€“ Ď€ in radians). Compensators are added to loops to add positive phase. This increases the

*phase margin*, the phase difference between the loop phase at a given frequency and â€“180

^{o}, where the loop oscillates. Therefore, the general feedback design goal is to keep the loop phase above â€“180

^{o}at

*f*for a positive phase margin.

_{T}Ideally, a compensator would contribute only zeros and no poles, but real analog circuits always have as many or more poles than zeros. (There are ways of circumventing this at a system level by paralleling circuits, such as in the PID compensator. And in the platonic world of DSP, zeros can be programmed without poles – but not in real-time!) The lead-lag compensator has an undesired pole that accompanies the desired zero. The design challenge in using this circuit for compensation is to place the zero where the additional (positive) phase is needed while placing the pole at a higher frequency that is not critical to the loop dynamics, preferably a decade above *f _{T} * .

To separate the pole and zero, the time constants must be separated by making *R _{2} * <<

*R*. However, this also makes the divider quasistatic gain << 1. This can be beneficial or not, depending on the loop. For loops that oscillate (or ring excessively) because they have too much quasistatic loop gain,

_{1}*GH*, not only does the zero add phase, the reduction in

_{0}*GH*by the divider pulls the Bode magnitude plot downward. As its magnitude decreases with frequency,

_{0}*f*decreases by moving to the left on the graph (shown below) – down to where there is not as much phase delay and the loop is more stable.

_{T}On the other hand, if the loop has too many poles but the loop gain must be kept what it is to meet precision (quasistatic error) requirements, then the lead-lag compensator is an inadequate remedy. The zero can be used to cancel an unwanted pole, but the compensator pole at a somewhat higher frequency remains. In effect, the compensator merely shifts a loop pole to a higher frequency, though not by more than a decade. And this is sometimes too little to matter. Therefore, the lead-lag compensator is best used when both an additional zero and reduced quasistatic gain will benefit the control situation.

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