Just in time for the Super Bowl and like the “Stub Hub” commercial below, in Figure 1, “You can’t have your Fan-out in here”. So what’s all this hype on Fan-out Wafer Level Packaging (FO-WLP)?

FAN IN WLP

First, let us define Fan-In WLP.

Fan In WLP means the flip chip interconnects are within the outline of the die as shown in Figure 2. Typically, integrated circuit die have peripheral I/O bonding pads, which are routed to a “X-Y” grid in rows and columns as shown in Figure 2. This is accomplished by adding another thin film conductor layer over a polyimide passivation called a redistribution layer (RDL).

Fan Out WLP means that the flip chip interconnects extend outside the outline of the example 3 mm die as shown in Figure 4. By extending the connections outside the die outline, a reduced I/O pitch is obtained.

WHY IS FAN OUT WLP SO IMPORTANT_2,3 ?

• Eliminates die interconnect (bumps and wire bonds) and substrate
• Excellent Electrical Performance – Shorter interconnects = Lower parasitic
• Eliminate interconnect stress and ELK (extreme low dielectric constant) crack delamination issues
• Fine Line/Space (L/S) for better RDL “route-ability”
• Finer pad pitch on die than flip chip
• Thin package, Smaller Form Factor, Potential System in Package (SiP), Multi-die, 3D Solutions
• – High integration – Heterogeneous chips including passives and /or Integrated Passive Devices (IPD)
• With die size reduction and higher pin count manufacturers will have two options:
1. Reducing ball pitch in order to have more connections within the die surface
2. Going Fan-Out and allowing an easier redistribution
• Since pitch reduction is very challenging, Fan-Out approach is offering a good compromise on next level (board) surface mount technology (SMT)

Conclusion:

Dan Tracy, SEMI, stated, “packaging is a key enabler of functionality in the mobile space ─ due to thin, small form factor multi-die and SiP applications growing. He also stressed that Fan-out wafer-level packaging (FO-WLP) is disruptive and will have a significant impact on the consumption of semiconductor packaging materials in the coming years.”

References

1. “Overview of Fan-out Wafer Level Package (FO WLP) and Fan -out Panel Level Package (FO-PLP)”, Charlie Lu, Altera
2. “Introduction to Fan-Out Wafer Level Packaging” Beth Keser, Qualcomm
3. Introduction to Advanced Microelectronic Packaging Technologies Course/Training, TJ Green Associates LLC. See description below