Ottawa, CanadaZarlink Semiconductor Inc. is sampling a range of integrated analog/digital PLLs (phase-locked loops) that meets all Synchronous Ethernet timing requirements, including the latest recommendation from the ITU-T (International Telecommunications Union).
Consented in June 2007, the ITU-T G.8262 recommendation (former G.paclock) outlines the minimum performance requirements for timing devices used to synchronize networking equipment that uses Synchronous Ethernet.
Synchronous Ethernet technology is being deployed in DSLAMs (digital subscriber line access multiplexers), routers, MSSPs (multi-service switching platforms), PON (passive optical network) and multi-service access equipment to enable voice, data, video and legacy services over a converged, high-bandwidth, Synchronous Ethernet link.
Zarlink's latest devices are built on the previously released ZL30107 and ZL30120 Gigabit Ethernet line card synchronizers. These second-generation devices of multi-rate, 1 GbE and 10 GbE analog/digital PLL products support all Ethernet frequencies with the option to support independent transmit and receive timing paths.
Zarlink's Synchronous Ethernet products support 1-GbE and 10-GbE frequencies or SONET/SDH frequencies. The devices also feature both single-ended and differential outputs.
Integrated dual PLLs in one package support transmit and receive timing paths, allowing the devices to seamlessly convert backplane and PHY clocks. In the transmit path, the products support rate conversion from standard telecom or Ethernet frequencies and provide jitter attenuation to generate a low-jitter Ethernet clock for the PHY.
In the receive path the products rate convert the Synchronous Ethernet recovered clocks to the backplane frequency, which then feeds back to the system timing card. In comparison, competing approaches would require multiple devices to implement transmit and receive timing paths.
Zarlink Semiconductor, 1-800-325-4927 or 1-858-675-3400, www.zarlink.com