A key challenge to the ultra-miniaturization of electronic systems is power management. As any EE knows, when overall system sizes shrink the amount of area available for energy storage and energy conversion shrinks with it. This is happening in many market-growing applications, such as implantable medical devices, Internet-of-things electronics, and wearable electronics. While the size of the electronics continues to scale, the batteries and capacitors required to store energy are not keeping up. The consequence is that often times the area required for energy storage and power management dominates the overall form factor of the final product.
Due to these area limitations energy must be stored in an efficient form. Often times the most efficient form is at a higher potential and with significant noise components. A voltage regulator – such as an LDO – is then required to regulate this supply voltage down to the level at which the system operates.
A key figure of merit in low power LDO design is current efficiency. Current efficiency is defined as the ratio of Iload to Itotal . This ratio is the percentage of overall power drawn from the power supply that is delivered to the load. For high power applications it is common for this number to exceed 99 percent. However, this is very different in low power design. If, for example, the total load current is 10uA, every 1uA of quiescent current in the LDO results in a 10% drop in current efficiency. In an already power constrained system this loss in efficiency can be catastrophic. As such, design methods that minimize the overall LDO quiescent current are critical. A properly designed LDO will maintain overall system efficiency and long battery life, minimizing the need for large energy storage elements.
A Short LDO Design Overview
Figure 1 shows an LDO block diagram utilizing an NMOS pass transistor. Consider applications where the unregulated power supply voltage (Vsply ) is much greater than the regulated output voltage (Vreg ). Here, a simple NMOS pass transistor architecture is usually the best choice.
This architecture has many desirable properties, two of which are trivial frequency compensation and a small FET area. A small FET area is a result of the higher mobility of charge carriers in NMOS FETs (electrons) versus that of PMOS FETs (holes). The ease of frequency compensation is due to the dominant pole being at the gate of the NMOS pass transistor instead of at the output node.
LDOs are typically two pole systems, with some architectures including a zero and / or an additional high frequency pole. The NMOS LDO shown in figure 1 is a simple two pole system. Therefore, stability is achieved by setting the frequency of pole P1 more than one decade below pole P2. As long as the two poles, P1 and P2, are well separated this LDO will be closed-loop stable. This is assuming that the error amplifier is a simple OTA with a single dominant pole at the output node. Once the output capacitor size (Cout ) is determined (set by high frequency load transient requirements, such as digital logic switching), pole P1 can be calculated. P1 is set by the product of the error amplifiers output impedance (ro ) and the compensation capacitor (Cc ). By increasing ro we are able to simultaneously achieve low P1 frequency and high loop gain, both very desirable traits.
It is important to remember that in an OTA design, high output impedance does not cost extra current just extra area. This enables the OTA, and correspondingly the LDO, quiescent current to be the minimum value required for unity gain bandwidth. This is an application specific requirement that sets the base line for quiescent current in a traditional LDO architecture. In many applications a quiescent current of only 100nA to 200nA is sufficient. This results in a current efficiency that is greater than 98 percent. It is worth noting that slew-rate enhanced LDOs are capable of going below this minimum current, but at a significant cost in terms of size and complexity.
Therefore, in an NMOS LDO, both stability and low quiescent current go hand-in-hand. But nothing comes for free. The NMOS LDO has one very large shortcoming. The minimum supply voltage (or overhead voltage) is Vgs(MN) + Vsat(MN) + Vreg which is approximately equal to 2Vsat(MN) + Vth + Vreg . Even if a native threshold NMOS transistor is used (Vth = ∼0V) this is double the overhead voltage of using a PMOS pass transistor. This is a major shortcoming that prevents the NMOS LDO from being used in many applications. It is also worth noting that use of a native threshold NMOS pass transistor is typically not advised. This is because across process corners these devices are very difficult to fully turn off, resulting in Vreg drifting up.
The alternative to an NMOS LDO architecture is a PMOS LDO. The PMOS LDO has the distinct advantage over the NMOS LDO of true “low-dropout” operation. This topology is capable of regulating the supply down to just one Vsat over the output voltage (<100mV is readily achievable). This, however, comes at the cost of significantly more challenging design tradeoffs. Many of these design tradeoffs are the consequence of pole position P1 and P2 swapping locations. While on the surface this seems like a small difference, it actually has very large implications to error amplifier design and overall LDO quiescent current. These implications and more will be covered in a future post to come soon.
In Low Power LDO Design Techniques for Really Small Profile Applications, Part 2 we will look at a PMOS LDO architecture