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Low Power LDO Design Techniques for Really Small Profile Applications, Part 2

In our previous post Low Power LDO Design Techniques for Really Small Profile Applications, Part 1 , we reviewed LDO design tradeoffs using an NMOS pass transistor. This design approach is proven good to implement on next generation really small-profile applications. In particular, this includes applications where the unregulated power supply voltage (Vsply ) is much greater than the regulated output voltage (Vreg ). Example applications include miniature implantable medical devices, Internet-of-Things devices and more. Here, a simple NMOS pass transistor architecture is often the best choice. However, in applications where Vreg approaches Vsply , a PMOS LDO architecture is often required.

As referenced in Figure 2 below, there are several differences between the PMOS and NMOS LDO architecture. The focus here will be on the pole position P1 and P2. The dominant pole is now required to be at the output of the LDO, with the secondary pole at the pass transistor (MP) gate. While on the surface this seems like a small difference, it actually has very large implications to error amplifier design. We are no longer able to achieve high loop gain and low dominant pole frequency simply by increasing ro .

Figure 2

LDO block diagram with PMOS pass transistor.

LDO block diagram with PMOS pass transistor.

The question to ask is why are we not able to set the pole on the gate of MP as the dominant pole? From a pure frequency stability stand point (that is, not thinking about circuit function but only system stability) this is perfectly fine. However, we should look at what is happening on the pass transistor gate from an AC perspective. If so, we see that an AC ground is formed on this node as the error amplifier’s gain rolls off. For an NMOS pass device this turns MN off at high frequency, exactly what we want, from a PSRR perspective. For a PMOS pass device this AC ground turns MP on at high frequency. This potentially creates a case where supply noise is no longer attenuated but, instead gained up (think of it as a common-gate amplifier). Since this is a highly undesirable operating condition, the two poles must be set as shown in Figure 2.

If we think of MP in Figure 2 as a common-source amplifier, the minimum voltage that must exist from drain to source for proper operation (that is, to extract gain from MP) is Vsat . If required, this can be designed down to < 100mV. The penalty for using a PMOS pass transistor is increased difficulty in frequency compensation (in part for previously covered reasons). The topic of PMOS LDO frequency compensation is the subject of many books and professional journal publications.

A Unique Approach to Frequency Compensation in Micro-Power LDOs

What we are interested in for our current focus is how to take advantage of micro-power load requirements to simplify frequency compensation. One standard method for simplifying frequency compensation in the architecture illustrated in Figure 2 is to use an external capacitor for Cout . This allows for a 1μF (or greater) capacitor to be placed on this node, pushing pole P1 to very low frequencies for all required load conditions. It is then relatively simple to keep poles P1 and P2 well-spaced. Thus, the LDO remains closed-loop stable. However, in pin constrained applications (as many micro-power applications are) the luxury of an off-chip capacitor is not always available. As such, we need a method for frequency compensation that uses only the available on-chip capacitance. A typical range for on-chip capacitance is roughly 500pF to 1nF.

One such method is shown in Figure 3. This approach utilizes a high gain error amplifier implemented with a large output resistance similar to that used in the NMOS LDO. To prevent the pole associated with the large output resistance from becoming the dominant pole, a unity gain buffer is inserted between the error amplifier and the PMOS pass transistor. This buffer serves two purposes: low input capacitance (Cib ) and low output resistance (rob ). The key shortcoming to this method is it generates a third pole in the system.

Figure 3

Block diagram for Micro-Power LDO using a PMOS pass transistor.

Block diagram for Micro-Power LDO using a PMOS pass transistor.

The low input capacitance prevents pole P2 from becoming the low frequency dominant pole. It allows us to obtain high loop gain by implementing the error amplifier with large ro . The low output resistance prevents the pole at the gate of MP (P3) from becoming the low frequency dominant pole. This low output resistance requirement becomes even more important when MP is large. However, because our specific application is for micro-power load currents, MP does not need to be drastically scaled up. This means that the requirement for a low rob is not as stringent as the requirement for a low Cib .

While the unity gain buffer does result in added area, power, and complexity, the implementation may be as simple as a gain-boosted source-follower (“super source-follower”). The gains in system performance for this added area and power far exceed those gains possible by applying that same area and power to the error amplifier design. It’s up to the designer if the added complexity (risk) is worthwhile.

Note that the architecture in Figure 3 has the same RHP zero as that of Figure 2. The methods for canceling this zero are well documented and apply equally well to both applications. Two of the most common methods are to insert a nulling resistor in series with Cc or to implement Cc as indirect feedback (Ahuja compensation). The diagram in figure 3 is implementing indirect feedback.

As previously discussed, this architecture relies on the available on-chip capacitance to set pole P1 at low frequency. This is where the micro-power load assumption becomes critical. If, for example, the maximum average load current is 10μA, then the equivalent output resistance, assuming a 1V regulated output voltage, is 100kΩ. If we assume the available on-chip capacitance is 500pF, then the resulting output pole frequency (under max load conditions) will be roughly ~3kHz. While not as low as the frequency achieved with off chip capacitors, this frequency is low enough to keep poles P2 and P3 well-separated from P1 thus achieving closed loop stability.

Conclusion

We’ve covered the application of LDOs to micro-power load regulation. Such applications commonly arise in ultra-miniaturized systems. NMOS LDOs are the preferred architecture when sufficient supply headroom is available. However, when true low dropout operation is required a PMOS LDO must be implemented. These architectures are more difficult to frequency compensate, especially when the application is pin constrained and an off chip capacitor is not available. As covered, there is a unique approach to stabilizing a PMOS LDO when the application has micro-power load requirements. This approach allows us to take advantage of the many good properties of PMOS LDOs without requiring an excessively large on-chip (or off-chip) capacitor.

1 comment on “Low Power LDO Design Techniques for Really Small Profile Applications, Part 2

  1. etnapowers
    March 17, 2015

    “In particular, this includes applications where the unregulated power supply voltage (Vsply ) is much greater than the regulated output voltage (Vreg ). Example applications include miniature implantable medical devices, Internet-of-Things devices and more”

     

    I wonder the reason of this big difference, could you elaborate on this?

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