Cadence Design Systems announces the Cadence Low-Power Solution, a fully integrated flow for logic design, verification, and implementation of low-power chips. The Cadence Low-Power Solution integrates leading-edge design, verification, and implementation technology with the Common Power Format (CPF), an Si2 format for specifying power-saving techniques early in the design process, to deliver an end-to-end low-power design solution to IC engineers. By preserving low-power design intent throughout the design, the solution eliminates laborious manual work, reduces power-related chip failure, and provides power predictability early in the design process.
“This is a dramatic step forward for designers seeking low-power design capabilities,” said Dr. Chi-Ping Hsu, corporate vice president at Cadence. “This solution is the first to provide designers with the ability to automatically instantiate low-power techniques at the register-transfer level (RTL) using a common format, with the assurance that they will function correctly throughout the verification, front-end implementation and physical-implementation steps.”
“Advanced low-power design is one of NXP Semiconductor's core competencies and we have been a leader for the industry movement to develop integrated low-power methodologies and create open standards,” said Barry Dennington, senior vice president of SoC Design Technology at NXP Semiconductors.”In the past, we relied on proprietary solutions for specifying power intent to support our Islands-of-Power methodology, including dynamic voltage frequency scaling (DVFS), but now have experienced the advantages of the Common Power Format and Cadence's CPF-enabled software to optimize SoC power architectures in sophisticated, 65-nanometer, low-power ICs.”
“Demands for advanced low-power technologies have been growing in the ASIC/COT business,” said Shoji Ichino, general manager of Design Platform Development Division, Electronic Devices Business Group of Fujitsu. “We're now developing an ASIC low-power solution based on the Cadence CPF-based low-power flow, which we expect would enable the adoption of MSV/PSO technologies not only for high-end 90-nanometer and 65-nanometer designs but also for mainstream designs. We're planning to get the solution ready for Q2 CY2007.”
“The Cadence Low-Power Solution provides us with a single front-to-back process for implementing low-power designs,” said Gary Nacer, vice president of engineering at Sandbridge. “Earlier, we taped out chips with the Cadence Low-Power Solution and with the integration of verification capability for power shut-off design. We believe this flow will provide us the ability to deliver competitive low-power products with minimal risk.”
Low-power design techniques are moving to the mainstream as demand for power-saving devices increases. For instance, portable applications need longer battery life, which necessitates optimum power savings. The move to highly integrated, high-performance sub-90-nanometer silicon creates heat-management challenges which require power optimization throughout the chip; and large end-product applications, such as server farms, require power optimization at every level, to reduce overall energy consumption. Similarly, cost considerations related to packaging are also driving designers toward low-power design.
To meet these diverse requirements, designers are increasingly employing advanced low-power design styles such as power shut-off (PSO), multi-supply voltages (MSV) and state-retention power gating (SRPG). However, automation of these techniques has been fragmented, with different tools using different ways of representing low-power intent. As a result, designers have been forced to specify low-power functionality through a set of ad-hoc methods, causing power data to be entered manually, multiple times in a single design effort. This repetitious data entry is tedious, error-prone, and more importantly, makes predictability and verification of the design extremely difficult.
The new Cadence Low-Power Solution addresses these difficulties by establishing a single representation of the design's power intent in the CPF specification, facilitating IP re-use and RTL portability. This representation spans the Cadence Logic Design Team Solution and Digital Implementation solution ” used by logic designers, verification engineers and implementation engineers ” including plan and metrics-driven flow management, simulation, logic synthesis, equivalence checking, test, placement, routing and IR-drop analysis. This enables an entire multi-specialist project team to work from a common view of the design which includes the low-power intent. It also greatly improves design predictability and minimizes the risk of chip failure
Common Power Format and the Power Forward Initiative
A key enabler of the new Cadence Low-Power Solution is the integration of CPF. CPF provides a standard lexicon that is recognizable from design through verification and implementation, ensuring consistency throughout the flow.
CPF 1.0 has undergone comprehensive review by Power Forward Initiative (PFI) advisors who are leaders representing all segments of the electronics industry, including semiconductor, foundry, semiconductor equipment, systems and electronic design automation companies. PFI advisors have provided more than 500 inputs that have been incorporated into CPF 1.0, which was contributed to the Si2 Low Power Coalition (LPC) in late 2006. Going forward, the LPC will be responsible for the evolution of CPF. The LPC has reviewed CPF 1.0 and, following the Si2 standardization process, has provisionally approved CPF as an Si2 specification.
“The Low Power Coalition has unanimously chosen to embrace the technology in CPF 1.0, making it broadly available to the industry at large,” said Steve Schulz, president and CEO of Si2. “This announcement clearly demonstrates the wide applicability of CPF across low-power flows and highlights the potential for interoperability among diverse tools from one or multiple vendors.”
As a Cadence project Torino milestone, the Cadence Low-Power Solution is available today and is scheduled to incorporate power-aware flow support for additional Cadence technologies throughout the year. Other project Torino deliverables will be announced throughout 2007.
More information about the company, its products, and services is available at www.cadence.com.