As I was sitting listening to a presentation on JESD204B recently, I reminisced back a few years ago to a period where LVDS (low-voltage differential switching) began overtaking CMOS.
I thought to myself that JESD204B looks to be on a similar path today. First, a quick overview. A CMOS I/O interface consists of individual single-ended logic signals. LVDS changes these to a pair of signal lines operating 180° out of phase (hence, differential). Differential signaling results in better noise immunity and can therefore typically operate at lower power levels for an equivalent signal-to-noise ratio. The JESD204 standard addresses sending and receiving data over a serial link, typically from an ADC to an FPGA or an ASIC. Additional revisions addressed details regarding the clock and multiple data signal paths (“lanes”) and issues regarding lane synchronization.
Obviously, there is a bit of reluctance out there on the part of system designers to make such a large change in the interface between the converter and their FPGA or ASIC. After all, this is part of the design that should be a given, right? It is often taken for granted that it should work, and well, that is should work pretty easily. Looking at the bigger picture, making this change requires engineering effort, time, and money.
However, as technologies push forward and system bandwidth requirements get higher and higher, converter sample rates must also push faster. There comes a point where LVDS is no longer practical. While the current and power consumption remain relatively flat for LVDS, the interface has an upper speed bound. This is due to the driver architecture as well as the many data lines that must be synchronized to a data clock.
With a 12-bit converter running at 200 MSPS, Table 1 show that CML (current mode logic) output drivers used in JESD204B start to become more efficient in terms of power consumption. CML requires less number of output pairs per a given resolution than LVDS and CMOS drivers due to the serialization of the data. The data in the table assumes a synchronization clock for each channel for CMOS and LVDS outputs and a maximum data rate of 4.0 Gbits for JESD204B using the CML outputs (less than half the limit of 12.5 Gbits for JESD204B). The reduction in pin count using JESD204B is significant.
Now, let's take this one step further and look at a 12 bit converter running at 2.0GSPS. Table 2 gives us an even better picture of the advantage of using JESD204B. For this example, we won't even look at CMOS because it is just completely impractical to try to use a CMOS output interface with a gigasample converter. In this case, we'll limit the number of converter channels to four. In order to keep the data rate within the limits of most FPGAs available today, two LVDS output pairs are needed for each bit. As you can see, the complexity in the output routing is much reduced for JESD204B due to the reduction in the number of output pins.
So, is LVDS really dead? Probably not. There is still a large market for MSPS range converters, but LVDS beware, JESD204B is coming fast!