Over the years, various technologies have been used to transmit signals over backplane busses. As speeds increase to cater to the ever-growing volume of telecom and datacom traffic, the limitation of the older, single-ended and emitter-coupled logic techniques becomes apparent.
Multipoint, low-voltage differential signaling (M-LVDS) is an interface standard similar to LVDS. It provides the benefits of high-speed, low-power, and low-EMI transmission solutions to today's bus applications. M-LVDS is suitable for data, control, synchronization and clock signals. (You can see a video on M-LVDS immediately below.) )
In today's backplanes, high-speed signals carrying the payload data are typically point-to-point (one driver and one receiver) interfaces. These connect various core chips such as ASICs, FPGAs, DSPs, and similar. Properly terminated point-to-point interfaces offer the best performance for high-speed signals. Signaling levels used can be PECL, CML, VML and LVDS with speeds going up to 4Gbps and higher, Figure 1 .
Figure 1: Driver level comparison
(Click on image to enlarge)
LVDS, which uses a simple termination scheme involving only one termination resistor placed at the receiver, can also handle multidrop signaling. This involves one transmitter and multiple receivers sharing the same differential transmission line. M-LVDS is an extension of LVDS that allows multiple drivers to share the same half-duplex bus.
LVDS (TIA/EIA-644A) is a well-known interface standard for point-to-point and multidrop applications that can be considered a speed upgrade to RS-422. M-LVDS (TIA/EIA-899) brings the benefits of LVDS (high speeds, low-power consumption, low EMI, simple termination, and industry standardization) to bus applications. It can be considered as a high-speed upgrade to RS-485 for common telecom applications over backplane (FR-4 material) traces or cables. M-LVDS provides robust signal integrity, hot swap, and built-in failsafe support.
LVDS provides a driver current output of 3.5 mA. M-LVDS triples this to 11.3 mA and reduces the voltage input threshold from 100 mV to 50 mV, thus providing more robust signal integrity. For standard-intended multipoint applications, with 100-ohm termination resistors at both ends of the bus resulting in an effective 50-ohm resistance, the signal voltage swing is 565 mV versus a typical LVDS swing of 350 mV, Figure 2 .
Figure 2: 200 Mbps signals over 20m CAT5, point-to-point interconnection, for M-LVDS (left) and LVDS (right)
(Click on image to enlarge)
For point-to-point cable applications, current IC output stages can still provide enough current over a single 100-ohm termination to produce a voltage swing of 900 mV to 1000 mV. This exceeds LVPECL levels of 800 mV.
M-LVDS ICs are used for clock and synchronization signal distribution up to 125MHz. They also are used for data and control signals with speeds up to 250 Mbps. Multipoint-LVDS can support all the most popular line circuit interface configurations mentioned above.
Fan-out buffers are a special adaptation of the point-to-point configuration. One source signal is copied on multiple driver outputs of the IC, Figure 3 . This arrangement is the classical means for centralized clock distribution. Dedicated fan-out buffers with M-LVDS outputs are now available. These are very popular in wireless infrastructure designs where clock signals originating from a centrally located control card radiate over the backplane to target ICs on other connected cards.
Figure 3: Standard interface configurations for fan-out buffers
(Click on image to enlarge)
The multipoint bus topology is particularly effective for clock and control signals. Decentralized clocking solutions, where the master source clock can be provided by any of the peer nodes on the bus, can use a multipoint bus configuration. Specialized, half-duplex transceiver devices are available to support these needs. M-LVDS is so well suited for clock management in telecom backplanes that it is used in ATCA and microTCA systems.
ATCA uses M-LVDS for a synchronization pulse at 8 kHz, clock distribution at 19.44 MHz, and a third user defended signal at a frequency up to 100 MHz. These three signals are duplicated on redundant lines. For these applications dedicated driver and receiver devices can be used.
Wherever two or more drivers are operating on shared bus, take designers must take special precautions to avoid damage to electronic components due to two or more transmitters being active at the same time. The following three contention provisions are provided for in the M-LVDS standard:
- IC devices must limit the bus voltage in a range from zero to 2.4 V.
- Drivers are short circuit limited to 43 mA.
- Drivers are tested with 32 contending nodes.
This accommodates most standard backplane applications. By using M-LVDS IC devices, the designer avoids the need to provision such safeguards using glue logic and additional external components.
Hot swapping, or live-insertion support built into interface ICs is very important for backplane applications. Datacom and telecom service providers need to have the ability to swap out cards for repair or standard maintenance without disruption to their end-customers. The ability to remove and replace backplane cards while the system in normal operation is critical. ICs and other components must not be damaged during insertion onto a live operating bus. It is also important to avoid interference with ongoing bus operations during the swapping event.
M-LVDS ICs offer hot-swap support by means of three key features:
- Glitch-free drivers.
- High-impedance receivers. These receivers do not draw current until they are properly charged up and ready to engage with the bus.
- ESD protection up to 8 kV human body model.
Failsafe support in the context of interface ICs refers to the ability to detect undesirable conditions presented to the differential receiver. These conditions can be open circuit, short circuit and absent signal. In typical differential receivers, such conditions may allow the receiver to process random noise on the input as a proper valid signal.
This can cause switching around the usual standard 0 V differential-trigger level and provide illegitimate output results. It will not be apparent to the end user for some time that these outputs are faulty, and this delay in recognition will disrupt the correct operation of the end-equipment and disrupt end-customer service.
M-LVDS Type-2 receivers provide a 100 mV offset to ensure that any input signals resulting from a failsafe condition, such as a disconnected cable, will result in the output of a known logic state. The sustained output of a constant logic level over time allows the service provider to recognize and alert engineers to a problem in the transmission line. M-LVDS Type-1 receivers offer standard 0 V levels and so offer faster and more symmetrical switching, which can be important for maintaining a specified clock duty cycle, for example.
M-LVDS fills a space in interface standards between LVDS, LVPECL and RS-485. The TIA/EIA-899 (M-LVDS) specification combines low-power, high-swing, and ease of design with robust features for bus applications such as failsafe, contention, and hot-swap handling. It is well-suited for clock distribution on backplanes as well as for point-to-point data transmission over cables. Originally conceived for multipoint buses, M-LVDS is the multifaceted industry standard that can be applied to multiple uses.
- For more information on TIA/EIA-899, go to http://www.ti.com/mlvds.
- For more information on this and other interface standards, go to http://www.ti.com/interface.
About the Author
David Mulcahy , Interface Marketing Manager, has been marketing analog ICs since 1995, when he joined Texas Instruments in Freising, Germany. Prior to joining TI, David worked for four years as a test engineer on scientific satellite projects in Italy.