In the first blog, Measuring an RMS value on a PSoC5, Part 1: Signal Acquisition, I showed how to acquire the signal and feed it to the Analog to Digital Converter (ADC). In Part 2, Measuring an RMS value on a PSoC5, Part 2: Squaring a Reading I used the Digital Filter Block (DFB) to square a number and accumulate those squares. As I mentioned before I came across the “Integer Square Root Calculator” component created by the PSoC community. Before you use it you will need to install it in PSoC Creator. First download it and unzip it. Then follow the directions in this video. If you download my PSoC Creator project you will need to delete the existing link to the square root component (it will be marked with a red exclamation mark in the User Dependencies window) in the project and reinstall it.

**Square Root**

After using the DFB, the square root component is stunningly trivial in its application. Just plonk it on the schematic and configure it. Obviously its internals are far more complex and you can get an idea of this in a blog “Implementing Complex Math using the Datapath”. You can only set up the component for the number of bits (I selected 24) and DMA/software access (I selected DMA only).

Figure 3-1 shows how everything is interconnected in generating the RMS value. This diagram was actually used during the development when there was no ADC and I was using data in RAM. All data are shifted around via Direct Memory Access so no processor time is consumed in the RMS calculation- well almost. I’ll get to that in a minute. Data are shifted from the RAM (in the full system from the ADC) to the DFB via the DMA_GetData component. The DMA fetch is triggered by a signal whose frequency is 16 times the frequency of the measured signal. In other words I am sampling 16 times in an analog input cycle. Each DMA fetch writes a single 16 bit number (actually a padded 12 bit) to the DFB.

The DFB will square it and accumulate it. Every 16 clocks the “EventCounter” counter clocks the SR register forcing a zero onto *in_1* input of the DFB and in its operation the DFB will square and add the 16^{th} number to the accumulator and notify the DMA controller (DMA_SaveData) that there is data. The 24 bit number is then “DMAed” to the SqRt component. SqRt trundles through the calculation and provides a 24 bit number in Q12.12 format. That is the most significant 12 bits are the integer part of the result and the less significant 12 bits are a fraction.

**Figure 3-1**

**The complete RMS system in realized in hardware. Note the addition of some external pins to aid with debugging.**

The DMA_SqRt writes the RMS value to a RAM location. Truth be told (you have been following, right?) the value stored is in fact four times the RMS value. Really! You didn’t forget that the calculation includes a division by the number of readings and if you move that outside the square root function it becomes a division by four. I could have added a four bit shift (for a divide by 16) at the output of the DFB, but that would have reduced the precision of the square root function and I could add a shift register in the hardware path to shift by two for a divide by four), but I would argue that it is not necessary. Once you have got the RMS value you are going to have to manipulate it further- you will need to convert it to a scaled reading or perhaps a 4-20mA output. It will improve the precision of the calculation by delaying the division and it is pretty easy to include a double shift somewhere in those calculations.

One of the nice things about developing with the PSoC is the ability to connect the internal signals to output pins to make measurements and to change connections by software configuration. Using Excel I generated the best sine wave a digital spreadsheet can do so I then could to simulate an input wave form by assigning the DAM_GetData to fetch that data from RAM. Later in the development I connected the DMA to the ADC to make real world measurements. Using artificial data I can tell you that to square a number takes 1.05µS and that the time from the 16^{th} word on data being written to the DFB to the result from the SqRt was 9.2µS. That is lightning fast compared to software calculations, to say nothing of settling time of traditional hardware approaches.

In addition using a sine wave with an amplitude of 511 (remember we are working with a 9 bit ADC derived from the 12 bit value) the error was 0.2%. On a triangular wave of the same amplitude the error was 1.2%.

**Tying It All Together**

Figure 3-2 shows the whole project interconnected. Of course you will see it much better in the project along with a few extra components to display the readings on a LCD.

**Figure 3-2**

**The complete RMS system in realized in hardware. Note the addition of some external pins to aid with debugging.**

I haven’t done extensive tests on the results but they do seem relatively stable and reasonable. As an example, for a 4Vpp sine wave- the peak would translate to 2V on the ADC with a full scale input of 2.048V. (2/2.048) * 511 equals 499. Remembering to multiply by 4 we get 1996 and then dividing by √ 2 gives 1411 which is 0x583. I was reading 0x579. A triangular wave of identical amplitude was expected to give 0x480 (remember Vpeak/ √ 3 gives a reading of 0x462.

It has occurred to me that the performance may be improved by introducing a zero crossing detector (using an on-board comparator) to synchronise the readings. That would necessitate shrinking the sampling period by a little so that the last sample in the cycle would occur before the zero crossing signal of the next sample. Another consideration would be with an 8 bit ADC value and 32 samples. I will certainly investigate this the next time I need to measure the RMS.

**Conclusion**

There you have it- another True-RMS measurement device. On the down side you only have a 9 bit ADC and the price of the micro is relatively high. It should be noted that only some versions of the PSoC5 and PSoC3 have the DFB component. On the up side the results are available faster than most other techniques and it requires no processing time from the host micro; all you need are 3 simple external components; and you have a micro that has almost all its software processing time available, plus its highly versatile set of peripherals.

Now I’m back to searching for a project to use as a vehicle to learn Verilog on the PSoC. Any ideas?

Unfortunately Dropbox has changed their implementation of public files. This has affected many, many instances where I have linked to my files. I am trying to update the links as I come across them. Dropbox will ask you to register in order to copy the file or open the file (you can only open the file once you log in)

In this blog this is the revised link to the project RMS1