SAN FRANCISCO — At the International Solid-State Circuits Conference (ISSCC) here, the Massachussets Institute of Technology (MIT) described a CMOS image sensor, based on a 3-D stacking technology.
Based on 0.35-micron technology, the 3-D imager is a 1-Mpixel (1,024- x 1,024-pixel) device fabricated with 8-mm pitch, per-pixel through-silicon vias (TSVs), according to MIT's paper.
3-D imagers from MIT can be ''tiled together to realize very large arrays.'' Applications include surveillance, reconnaissance, among others.
MIT's imager has two basic tiers, which consists of seven layers. The first two tiers are the 3-D imager. ''Tier 1 consists of 100 percent fill factor, deep-depletion photodiodes, thinned to 50-mm,'' according to the paper. ''Tier 2 consists of SOI-CMOS pixel readout and selection circuitry that is 3-D connected to Tier 1 photodiodes.''
The remaining five layers have a multi-chip silicon stack, which includes two silicon chips with 64 12b pipelined analog-to-digital converters, a timing sequencer, tile address encoder, bias generators, I2 C serial interface, and two 12b wide LVDS outputs running at 512-Mb/s.
The imager is connected to the stack via a gold stud bump array at a 500-mm pitch.