Mixed-signal designs combine the most powerful features and advantages of both analog and digital circuitry. One common mixed-signal architecture is a chain of analog signal blocks, each controlled by digital logic. These designs take advantage of the stability and algorithmic capabilities of digital logic to control traditional analog circuitry.
Because digital logic can be easily modified throughout a design cycle, it is often preferable to keep most of the “intelligence” of a control loop in the digital logic. The analog circuitry should be as simple and direct as possible. Decoders, delays, and other functions should be implemented digitally whenever possible.
Digital logic does not suffer from drift or process variation in the same sense as analog circuitry. Phenomena such as oscillation are much easier to control or prevent entirely. Certain functions – such as control loops that can hold a specific value indefinitely – become very easy to implement in logic. Such circuits are small in area, resistant to noise, and easy to implement.
A typical control strategy is illustrated in Figure 1 . An input signal is passed through some form of analog signal processing circuitry. The output signal is analyzed by the digital logic, and a digital control algorithm updates the behavior of the analog circuitry. Gain, offset, clamp current, and filter center frequency are quantities typically controlled in this fashion.
Figure 1: A conceptual view of a mixed-signal feedback loop.
As a specific example, we will use the automatic gain control circuit shown in Figure 2 . The input signal is assumed to be a simple sine wave, which is adjusted in amplitude by the analog signal processing circuitry. The (DC) gain block performs this example’s entire analog signal processing. It accepts a six-bit code, and adjusts the (DC) gain of the signal by ± 6 dB.
Figure 2: The Automatic Gain Control: DC block performs all analog signal processing
The comparator is the simplest example of a “digital signal analyzer,” and compares the output signal with a reference of 1.5 V. The amplitude of the signal is to be adjusted so that its lowest value just begins to trip the comparator. The block labeled IEC_Controller contains the digital control algorithm. The central idea behind this controller is simple:
1. Measure the fraction of clock cycles in which the comparator output is low.
2. Periodically compare this fraction with a desired target value.
3. If the count is too high, adjust the DC gain downwards. If it is too low, adjust the DC gain upwards.
The remainder of the circuit is a “dither detector,” embodied in the IEC_DitherDetector block, which is able to determine when the DC gain value has stabilized. After stabilization, the control loop’s output is locked. This prevents the circuit from wandering randomly between codes.
Digital Loop Considerations
Any control loop must have a target – a value or condition that is sought – and this AGC circuit was designed with an explicit target of 1 high comparator count per 256 clock cycles, or a duty cycle of about 0.4%.
This value was chosen because the resulting error – 0.4% – was deemed acceptable. Every application is different, however, so the dynamic range of error signals must be chosen carefully.
A counter called ComparatorCounter is used to count the number of clock cycles when the comparator is high. The control loop creates an error signal, called Error , by subtracting the target from the actual count.
The loop output is constrained to not overflow or underflow. In addition, each update event clears the ComparatorCounter , thus starting another 256-clock cycle measurement.
Multiple Feedback Loop Considerations
A control loop’s slewing behavior is somewhat inconsequential when it is the only control loop in a system, but becomes much more important to consider when it may interact with several other loops.
It is a well-known result of control theory that, when multiple control loops are used together, they should have time constants that are an order of magnitude different to minimize their interactions.
The time constant of a digital control loop is very easy to change. If the loop output is N bits wide, the error integrator can be made several bits wider, perhaps N+2. The least-significant bits are then considered fractional and left unused, effectively slowing the loop down. With a little extra logic, the time constant can also be made dynamic, changing in response to the status of other loops.
Dither and Settling
The word dither describes the condition of a control loop oscillating back and forth between two (or more) discrete output codes. This is normal behavior for these kinds of control loops, and in some applications it is of no consequence.
In applications where dither cannot be tolerated, a little extra logic can be used to eliminate it. The easiest way to detect dither is to look at the loop’s error signal. When the error signal is small, the loop is near its target. When the error remains small for a suitable length of time, the loop’s error integrator can be disabled, preventing further updates.
Determining when the error signal has been small for a “suitable time” implies some form of low-pass filtering. The simplest possible low-pass filter is a single-pole IIR (infinite impulse response) filter. These filters are easy to implement in digital logic.
Another (optional) counter may be used to give the loop even more time to fully settle, even after its filtered error signal becomes acceptably small. In this example, this counter is called SettleCounter , and it is cleared whenever the filtered error signal is too large. When the filtered error signal is acceptably small, it counts upwards, once per update event. When it reaches its maximum value, the control loop’s error integrator is stopped, and the loop’s output no longer changes.
The loop itself continues to run for all time – its error signal must continue to track changes in the input signal – but the output value is locked so that it cannot dither. When the input signal changes substantially, the filtered error signal will grow, causing the loop to unlock and begin re-acquiring the signal.
The behavior of the example circuit is demonstrated in Figure 3 . The output signal, Vout , is initially too large. The DCGain value slews downwards, one decrement per 256 clock cycles, until the Error signal nears zero. The AbsFilteredError signal lags the error signal, eventually dropping below the reacquisition threshold. Reacquire then goes low. After the SettleCounter reaches its maximum value, the LoopEnable goes low, and the loop output is locked.
Figure 3: Waveform output showing acquisition and locking
Mixed-signal control loops offer many advantages over traditional, fully analog control loops. They are easy to implement and provide guarantees on stability, particularly when coupled with a properly designed dither detector. The ability to “lock” the control loop is unique to digital logic, and is a tremendous asset.
The error integrator and loop error filter strategies represent building-block approaches that can be applied to many different problems. When possible, the strengths of both digital and analog design methodologies can be brought together to create novel control structures that are small, robust, and easy to implement.
About the authors
Warren Craddock is a staff mixed-signal design engineer at Intersil Corp. He specializes in control systems, digital signal processing, and design automation. He received his BSEE from Virginia Tech in 2001.
Tamara Schmitz is a senior principal applications engineer and global technical trainer at Intersil Corporation. She has a BSEE, MSEE and PhD in RF CMOS design from Stanford University.