The comments and replies to my blog post last month show that the topic of interleaved ADCs has a good bit of interest out there. Thanks for the great response. I enjoy the dialogue with you guys. The questions prompted me to think more on the benefits of interleaving and what applications might benefit from it.
There were also some questions on how many converters can be interleaved, so I thought I'd touch on that briefly. And there were some questions on the challenges of interleaving ADCs. Before we take a look at that, let's discuss some of the benefits.
The benefits of interleaving span multiple segments of the market. The most desired benefit is the increased bandwidth made possible by the wider Nyquist zone of the interleaved ADCs. Once again, we'll take the example of two 500MSPS ADCs interleaved to create a sample rate of 1000MSPS. Here is a representation of the much wider bandwidth allowed by interleaving the two ADCs. Note that fS is shown for one converter; the interleaved converter sample rate would be 2 X fS .
This creates advantages for many different applications. The system requirements in many designs inherently stay ahead of commercial ADC technology. No matter how high ADC sample rates get, the market seems to demand even faster rates. Interleaving allows for some of this gap to be closed. Military and aerospace applications are pushing for higher bandwidths to achieve better spatial recognition. Also, increased channel bandwidths are needed in backend communications.
As cellular standards increase channel bandwidth and the number of operating bands, increased demands are placed on the available bandwidth in the ADC. In some markets and applications, there is also a desire to move to direct RF sampling, so that the radio design has fewer stages and the demodulator can be removed. Having a high enough sample rate on the ADC also opens up the possibility of easing clocking requirements. It becomes possible to align the ADC and DAC clocks to make system design easier. In instrumentation and measurement applications, higher bandwidths are needed to acquire and measure signals.
An increased sample rate provides more bandwidth for these applications. It allows for easier frequency planning, and it reduces the complexity and cost of the anti-aliasing filter typically used at the ADC inputs.
With all these great benefits, one has to wonder about the price. As with most things, there is no such thing as a free lunch. Interleaved ADCs offer increased bandwidth and other nice benefits, but there are some challenges that arise.
How many converters can we put together? Let's take a simple look at the clocking requirements for interleaved ADCs. You may remember from my last blog the equation:
Solving this equation is pretty easy when m equals two. However, the clocking requirements become much more difficult when m equals, say, 8. Substituting for m and solving the equation for eight converters yields required clock phases of 0, 45, 90, 135, 180, 225, 270, and 315 degrees. That doesn't seem too bad if the input clock has a low frequency, but the whole point of interleaving is achieving a high sample rate.
A realistic case for the clock frequency is 1GHz. This means the clock circuitry must be able to divide the input clock down and create phases 125ps apart, and it must do so with accuracy. Any error or jitter on the clock will degrade performance.
There are other things to consider, as well. When two or more converters are interleaved, there are mismatches between individual converters. We also must consider the analog input bandwidth of the converter. How are these mismatches handled? What do we do about the analog input bandwidth?
But that's enough discussion for now. Stay tuned for more on interleaved ADCs. Have you had experience with high-speed ADCs? Have you tried to interleave them?