MSC Vertriebs offers lowest power SERDES capable FPGA

MSC Vertriebs GmbH is offering the Lattice ECP3 family which defines a new mid-range, value-based class of FPGAs, not only by further reducing costs, but also by reducing total power consumption by more than 50 percent for typical designs, compared to competitive SERDES-capable FPGAs.

To minimize power consumption the LatticeECP3 FPGA family uses variable channel lengths, optimized low-power transistors and improved routing defaults as well as algorithms. By making careful design choices and minimizing die size, Lattice can offer the benefits of high speed serial I/O and processing capabilities, without the power and cost premiums typically associated with these types of devices. With these features, the LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireless infrastructure and wireline access equipment, as well as video and imaging applications.

The low power, high value LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3G SERDES, DDR1/2/3 memory interfaces for low cost FPGAs and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family, as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17 K LUTs to 149 K LUTs with up to 586 user I/O. The Lattice ECP3 FPGA family offers high performance features like 3.2 Gbps SERDES with 10GbE XAUI jitter compliance and the ability to mix and match multiple protocols on each SERDES quad including PCI Express, CPRI, OBSAI, XAUI, Serial Rapid IO and SGMII/Gigabit Ethernet. The SERDES/PCS blocks have been designed specifically to enable the design of the low latency variation CPRI links that are found in wireless basestations with Remote Radio Head connectivity.

The Lattice ECP3 SERDES Blocks are compliant to the SMPTE Serial Digital Interface standard, with the ability to support 3G, HD and SD video broadcast signals independently on each SERDES channel. The triple rate support is performed without any oversampling technique, consuming the least possible amount of power.

The Lattice ECP3 family offers DSP blocks allowing up to 36×36 Multiply and Accumulate functions running at > 400 MHz. The DSP slices also feature innovative cascading ability for implementing wide ALU and adder tree functions without the performance bottlenecks of FPGA logic. 1 Gbps LVDS I/O, with Input Delay blocks, allows interfacing to high performance ADCs and DACs. Thanks to the advances in device architecture and the use of 65 nm technology the Lattice ECP3 familiy is suitable for high-volume, high-speed and low cost applications.

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